1 - Al Kossow's Bitsavers

4. Row address setup and hold timeThe row address setup time to the TMS4500A is guaranteed by the MC68000L6 address valid toAS low timing (tAVSU.tAV-AEL = tAVSL = 35 ns (MIN, MC68000L6 Spec.)The row address setup time to the DRAMs is given by:tASR == tAVSL - tRAV-MAV + tAEL-REL *where tRAV-MAV = Time delay, row address valid to memory address valid (MAX 4500A-15Spec.)thus,tASR = (35 ..:. 40 + 27) ns= 22 nsThe row address hold time to the DRAMs is guaranteed by the TMS4500A to meet - 20 or fasterspeed devices.5. Data valid to write enableIn both circuit configurations, data valid to write low is guaranteed by the MC68000L6. For the circuitin Figure 1 A this is accomplished by gating CAS with UDS and LDS to give an early write condition.For the circuit in Figure 2A R/W is gated with UDS and LDS to give a late write condition. Datavalid to write enable for both circuits is given by:tDS = tDOSL + tp32where tDS = Data setup timetDOSL = Data out valid to DS low (MIN, MC68000L6 Spec.)tP32 = Propagation delay (MIN, 74LS32 Spec.)ThustDS = (35 + 8) ns= 43 ns6. Read access time from CASThe required access time for both access and access grant memory cycles must be calculated.The read access time from CAS on normal access cycles for the gated R/W configuration (Figure 2A)is given by:wherethus,tCAC = 2.5(T) - tCHSLx - tAEL-CEL - tt(CEL) - tDICLtCAC = Access time from CAStAEL-CEL = Time delay, ALE low to CAS st~rting low (MAX 4500A-15 Spec.)tt(CEL) = CAS fall time (MAX 4500A-15 SpeG')tDICL = Data, in to clock low (MIN, MC68000~6 Spec.)tCAC = [2.5(166) - 65 - 150 - 15 - 25] n~= 1.60 nsThe read access time on access grant cycles for the gated R/W configuration (Figure 2A) is given by:tCAC = 2.5(T) - tCH-CEL - tt(CEL) - tDICLwhere tCH-CEL = Time delay, CLK high to access CAS starting low (MAX 4500A-15 Spec.)9-76