1 - Al Kossow's Bitsavers

R/W approach does a normal read-modify-write to the DRAM. The choice of these methods wouldprobably be determined by other factors in the system design; particularly the size of the memoryarray since the TMS4416 example would require less logic to implement but lends itself better tosmaller memory designs.The DTACK signal is derived by ANDing UDS, LOS, and R/W together, clocking ROY with a flip-flopand then DRing the two results. On normal accesses the ROY signal is high allowing either the UDS,LOS, o~' R/W signal to force DT ACK low. On access grant cycles the low ROY signal holds DT ACKhigh one clock period after the refresh cycle is complete. UDS, LOS and R/W are ANDed togetherso that on read cycles UDS and/or LOS force DT ACK low and on write cycles R/W forces DT ACKlow. This gating is necessary because UDS and LOS go low too late in the write cycle to provide sufficientDTACK setup time. It also provides the two DTACK pulses for read-modify-write cycles. Forthe MC68000L8/L 10 design DTACK is delayed with a flip-flop to provide one wait state.6 MHzCLK T ICLK+5V- _CLK_ RAS001- 4ACW RASO004AS ALE AO-A7~MC68000L6 L ill :---W48001-A1-A8 RAO-RA7 - CAS D046A9-A14CA1-CA6 ~ -G ~TMS4416A15CAO*001- 4MAO-004A16CA7*I~ASMA7 ~-A17 REN1 IG TMS4416 -001- 400400-015A18 csT I~ODS TMS4500A GLOS - ROY 19M54416CASR/W CAS RAS1,0DTA'Ci