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wherethus,fCLKfCLKtCACfCLK[1/2 (tCAC + TCLRL + tACL-CEL + tt(CEL) + TDVCU]-l X109Maximum 8088 clock frequencyCAS access time (MIN TMS4416-20 Spec.)[1/2 (120 + 165 + 90 + 15 + 30)] ns4.762 MHzA circuit configuration to interface dynamic memories to the 8088 microprocessor utilizing the TMS4500Adynamic RAM controller has been presented. The circuit design featured a 5 MHz 8088 interfaced to aTMS4500A-15 operating with no wait states. The memory array was implemented with TMS4416 dynamicRAMs for increased modularity.MOS MemoryApplications Engineering•Texas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.Texas Instruments assumes no responsibility for infringement of patents or rights of others based on Texas Instruments applications assistance or productspecifications, since TI does not possess full access to data concerning the use or applications of customer's products. TI also assumes no responsibilityfor customer product designs.9-68
Applications BriefTMS4500A/MC68000 INTERFACEThis application note provides several circuit configurations interfacing three speed rangesof the MC68000 microprocessor to dynamic RAM memory via the TMS4500A-15 dynamicRAM controller. The MC68000L6 operates with no wait states while the MC68000L8 andMC68000L 10 operate with one wait on normal memory access cycles. The memory arrayis organized as 32K words featuring the TMS4416 16K x 4 dynamic RAM arranged as tworows of 16K x 16 bits with each. row partitioned into 16K bytes of upper and 16K byteslower memory. The TMS4416 was used for its modularity advantage over X 1 DRAMs andupgradability to future 64K x 4 devices.Two approaches for controlling access to the upper and lower bytes of memory are given.The first approach (Figure 1 A) controls access to upper and lower memory by gating CASwith UDS and LDS providing an early write condition. Early write occurs when the W signalto the DRAM goes low prior to CAS low. Under this condition the data input to the DRAMis req'uired to be set up prior to CAS instead of prior to W, and the output buffers are disabledallowing the use of common I/O. This can be achieved on the TMS4164 by tying Dand Q together; the TMS4416 is a common I/O device. The second approach (Figure 2A)controls access to upper and lower memory by gating R/W with UDS and LDS providinga late write condition (CAS low prior to W low). There are definite advantages and disadvantagesto each of the implementations. From a system standpoint the gated CAS requiresa smaller number of gates than the gated R/W version but would degrade CAS access timewith the extra SSI gate (74LS32) delay. Another system criteria would be the choice ofmemory used with each implementation. For the gated CAS approach both TMS4416s andTMS4164s could be used with common I/O reducing layout signal routing complexity. Thegated R/W implementation restricts the use of common I/O when using TMS4164s due tolate write operation. In the late write cycle the Q outputs will go to an active state causingcontention between the processor and the memory for the data bus. To use TMS4164s withinthe gated R/W system requires that the Q outputs be externally buffered to allow a bidirectionaldata bus which adds extra circuitry for the buffers. The timing diagrams for Figures1 A and 2A are given in Figure 1 Band 2B, respectively.co0';:;m... Eo~.EU)co0';:;mo~C.c.«Both methods of upper and lower byte control allow the use of read-modify-write (TAS instruction)cycles but the operational response of the DRAMs is ~lightly different. A readmodify-writeis performed by first reading the data from a memory I~cation then writing databack to that location in the same memory cycle. The TAS instrJction (Test and Set anOperand) tests a byte bperand and sets the negative and zero flag~aCCOrdingIY; the highorder bit of the operand is set. This provides a means of sync ronization in multipleprocessor environments. Figure 3 shows the read-modify-write timi ~s for the gated CASand gated R/W implementations. The two methods for controlling memory access have theadvantages and disadvantages mentioned above plus another difference on read-modifywritecycles. The gated CAS approach actually does a page mode read then a page modewrite (two CAS cycles for a single RAS cycle) to the same memory location while the gated9-69
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SMYOOO2.,MOS MemoryData Book1984II
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ALPHANUMERIC INDEX TO DATA SHEETSSM
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TABLE OF CONTENTSALPHANUMERIC INDEX
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MOSLSIRAMs, ROMs, EPROMsSELECTION G
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If you want to give it a try for yo
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INTERCHANGEABILITY GUIDEPART 1 -ALT
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INTERCHANGEABILITY GUIDEFUJITSUMB 8
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INTERCHANGEABILITY GUIDEMOTOROLAMCM
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INTERCHANGEABILITY GUIDETOSHIBATMM
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INTERCHANGEABILITY GUIDESTATIC RAMS
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Alphanumeric Index, Table of Conten
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GLOSSARY fTIMING CONVENTIONS/DATA S
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GLOSSARY/TIMING CONVENTIONS/DATA SH
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GLOSSARY!TIMING CONVENTIONS/DATA SH
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MOSLSITMS411616,384-811 DYNAMIC RAN
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TMS411616,384·811 DYNAMIC RANDOM·
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1MS411616,384-811 DYNAMIC RANDOM-AC
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TMS411616.384·81T DYNAMIC RANDOM·
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zIiADDRESSES~!.....RASCASwDO"*. i,*
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TMS411616,384-81T DYNAMIC RANDOM-AC
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MOSLSITMS416165,536-81T MULTIPORT M
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TMS416165,536-811 MULTIPORT MEMORYf
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TMS416165,536-BIT MULTIPORT MEMORYs
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TMS416165,536-0IT MULTIPORT MEMORYc
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TMS416165,536·BIT MUL TIPORT MEMOR
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TMS416165,536 o BIT MUL TIPORT MEMO
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TMS416165,536·811 MULTIPORT MEMORY
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zI[~~~co,.. twiRL) _,RAS:::~ SI l L
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TMS416165,536·BIT MULTIPORT MEMORY
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~ ___TMS416165.536-BIT MUL TIPORT M
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0>~a~~i'i_';:;Z~~~d~c:::• s:~lTl~
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TMS416165,536-8IT MULTIPORT MEMORY1
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MOSLSITMS4164, SMJ416465,536-8IT DY
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TMS4164, SMJ416465,536-811. DYNAMIC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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SMJ416465,536-81T DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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TMS4164, SMJ416465,536·81T DYNAMIC
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TMS4164, SMJ416465,536·8IT DYNAMIC
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z~~gz~.J:>.c1J
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Z~d~~~~0,'...."CIIICCCD:3of. twIRL)
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MOSLSITMS4256. TMS4257262.144·8IT
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TMS4256, TMS4257262,144·8IT DYNAMI
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TMS4256, TMS4257262,144-8IT DYNAMIC
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TMS4257262.144·8IT DYNAMIC RANDOM
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TMS4256, TMS4257262,144·BIT DYNAMI
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TMS4257262,144·81T DYNAMIC RANDOM
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Z~d~~~~.!..JcoNOTE:'CIIICO(1),- twI
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i:Z~d~~z~+:>0Co ......"CCICCCD:3og.
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MOSLSITMS4416. SMJ441616.384·WORD
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TMS4416, SMJ441616,384·WORD BY 4·
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TMS441616,384-WORD BY 4-BI1 DYNAMIC
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TMS441616,384-WORD BY 4-BIT DYNAMIC
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SMJ441616,384·WORD BY 4·BIT DYNAM
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SMJ441616,384-WORD BY 4-B11 DYNAMIC
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1MS4416, SMJ441616,384·WORD BY 4·
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TMS4416, SMJ441616,384·WORD BY 4·
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z~~~z@towRAs-{rCASAO·A7wDQG:::'.!A
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1:'QltC(()3oc..(()C3~~n_:::Z~~~;;;
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MOSLSITMS446465,536-WORD BY 4-BIT D
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TMS446465,536-WORD 8Y 4-81T DYNAMIC
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TMS446465,536·WORD BY 4·BIT DYNAM
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1MS446465,536·WORD BY 4·B11 DYNAM
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TMS446465,536·WORD BY 4·BIT DYNAM
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RASCAS----{! '.,ReIVIH i~VIL I tRLC
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~~~n_;;;z~~. ~~tTlg ;O~d ;;;t::=z~@
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~Z~~iZ~tw '"[:;-~~~~~:TCDCO ".;:r0~
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MEMORY SUPPORTLSITMS4500ADYNAMIC RA
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TMS4500ADYNAMIC RAM CONTROLLERpin d
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TMS4500ADYNAMIC RAM CONTROLLERarbit
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TMS4500ADYNAMIC RAM CONTROLLERswitc
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TMS4500ADYNAMIC RAM CONTROLLERacces
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TMS4500ADYNAMIC RAM CONTROLLERoutpu
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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•••••MOSLSI65,536 X 4 Org
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TM4164EC465,536 BY 4·BIT DYNAMIC R
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MOSLSITM4164EL965,536 BY 9·BIT DYN
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TM4164EL965,536 BY 9-BIT DYNAMIC RA
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••••••••0MOSLSI65,5
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TM4164FL865,536 BY 8·BIT DYNAMIC R
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MOSLSITMS2516. SMJ251616.384-BIT ER
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TMS2516, SMJ251616,384-BIT ERASABLE
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TMS251616,384·BIT ERASABLE PROGRAM
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SMJ251616,384-BIT ERASABLE PROGRAMM
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o 441MS2516, SMJ251616,384·B11 ERA
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MOSLSITMS2532, SMJ253232,768·BIT E
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TMS253232,768-BI1 ERASABLE PROGRAMM
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MOSLSITMS2564, SMJ256465,536-BIT ER
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TMS256465,536-BIT ERASABLE PROGRAMM
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TMS2564 r SMJ256465 r536-BIT ERASAB
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MOSLSITMS2708, TMS27L08, SMJ2708, S
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TMS270B, TMS27LOBSMJ270B, SMJ27LOB1
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TMS2708. TMS27L081024·WORD BY 8·B
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SMJ2708, SMJ27L081024·WORD BY 8·B
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TMS2708, TMS27L08SMJ2708, SMJ27L081
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MOSLSITMS27162048·WORD BY 8·BIT E
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TMS27162048·WORD BY 8·BIT ERASABL
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TMS27162048-WORD BY 8-BIT ERASABLEP
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TMS2732A32,76B-BIT ERASABLE PROGRAM
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TMS2732A32,768-BIT ERASABLE PROGRAM
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TMS2732A32,768·BIT ERASABLE PROGRA
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MOSLSITMS276465,536-BI1 ERASABLE PR
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TMS276465,536·BIT ERASABLE PROGRAM
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MOSLSITMS27128131,072·BIT ERASABLE
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TMS27128131,072·BI1 ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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MOSLSITMS46648192·WORD BY 8·BIT R
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TMS46648192·WORD BY 8·BIT READ·O
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MOSLSITMS47324096~WORD BY B·BIT RE
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MOSLSITMS47648192·WORD BY 8·BIT R
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MOSLSI, TMS49648192·WORD BY 8·BIT
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MOSLSITMS4712816,384·WORD BY 8·BI
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TMS4712816,384·WORD BY 8·BIT READ
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TMS4712816,384-WORD BY 8-BIT READ-O
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MOSLSITMS4725632.768·WORD BY 8·BI
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TMS4725632.768·WORD BY 8·BIT READ
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MOSLSITMS2114, TMS2114L1024·WORD B
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TMS2114, TMS2114L1024·WDRD BY 4·B
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TMS2114. TMS2114L1024·WORD BV 4·B
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ADVANCED MEMORYDEVELOPMENT•Fast A
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TMS2150CACHE ADDRESS COMPARATORabso
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TMS2150CACHE ADDRESS COMPARATORPARA
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MOSLSITMS40162048·WORD BY 8·BIT S
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TMS4016204H-WORD BY H-BIT STATIC RA
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TMS40162048-WDRD BY 8-BIT STATIC RA
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MOSLSITMS4044, TMS40L444096-WORD BY
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TMS4044, TMS40L444096·WORD BY 1·B
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TMS4044, TMS40L444096·WORD BY l·B
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MILITARYCMOSLSISMJ55172048-WORD BY
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SMJ5517204a·WORD BY a·BIT STATIC
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SMJ55172048·WORD BY 8·BIT STATIC
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SMJ55172048-WDRD BY 8-BIT STATIC RA
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SMJ5517204B·WORD BY B·BIT STATIC
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However, the TMS 4164 provides the
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EXPANSION OF 3242 FOR 256-CYCLE REF
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•9-6
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PAD OPENINGIN OVERCOATPADMETALPADME
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Figure 5 shows how the driver outpu
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cpI UO,leWJOJUI suo'le:>!ldd"f\)W(3
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The falling edge of RAS causes R 1
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~--------::~~:~:~~~:--------~~7,34(
Page 368 and 369: J-Lead AdvantageTexas Instruments P
Page 370 and 371: Surface Mount Component Availabilit
Page 372 and 373: fiSECONDARYVAPOR(VAPOR BLANKET)..Fi
Page 374 and 375: l>'C'2.ri'Q),..o·:::Jen5'....... o
Page 376 and 377: l>"C'2..(i"Dl...0":=(I)5"....o...3D
Page 378 and 379: An external refresh counter has bee
Page 380 and 381: l>'C'CC:)"Q).-+o·::::sen:ro ... ""
Page 382 and 383: uo!~ew"oJul suo!~ea!ldd"CD .,.., w7
Page 384 and 385: DOTCLOCKCLOCK ACLOCK C2 xWCLKRAS (A
Page 386 and 387: B. If dynamic RAM refresh is enable
Page 388 and 389: •9-38
Page 390 and 391: The TMS4416/TMS4500A board is arran
Page 392 and 393: RAS ~CAS \ I2AI \ I '-2BI '-iiD1Ro2
Page 394 and 395: 9-44
Page 396 and 397: ALEACXRASMAO-MA7CASFIGURE 1 -ALE LE
Page 398 and 399: The ALE high to ClK low time is giv
Page 400 and 401: ClKALEACXRASMAO-MA7CASREFREQROY•
Page 402 and 403: CDinN~1~12 MHzClKINClKOUTWE/iOclKRD
Page 404 and 405: UO!leWJOJUI SUOlle:ludd"com~'~,i'74
Page 406 and 407: coen(J)CLOCKWRITEREADROYALEA14-A5MS
Page 408 and 409: . Access Grant CyclesThe precharge
Page 410 and 411: whereta(C)tp(BFR)(-103 + tc2 - tp(B
Page 412 and 413: •9-62
Page 414 and 415: tt(REH)TCHLLtAEL-RELRAS rise time (
Page 416 and 417: . Refresh CyclesOn refresh cycles t
Page 420 and 421: R/W approach does a normal read-mod
Page 422 and 423: II(0~""6 MHzI UO!leWJO,ulSUo!le:l!l
Page 424 and 425: ClKAlE.ACR\ ,----\,\ ,----R/W\ ,---
Page 426 and 427: 4. Row address setup and hold timeT
Page 428 and 429: CLKrWRITE -------I.~ ..~---REFRESH-
Page 430 and 431: The read access time on access gran
Page 432 and 433: implementations in order to relieve
Page 434 and 435: "C'2..c:rm...o·j(I)....5'o3...mo·
Page 436 and 437: RELATIVE MEMORY SIZEARCHIVAL STORAG
Page 438 and 439: increments till satisfied. This pro
Page 440 and 441: In the example shown in Figure 5, t
Page 442 and 443: »'C"E..crQ)r+0':::Jtil:;-....o...3
Page 444 and 445: •9-94
Page 447 and 448: 184LOGIC SYMBOLS1. INTRODUCTIONEXPl
Page 449 and 450: LOGIC SYMBOLS4.DIAGRAMATIC SUMMARYI
Page 451 and 452: lOGIC SYMBOLSWhen RAS goes low, it
Page 453 and 454: Alphanumeric Index, Table of Conten
Page 455 and 456: MECHANICAL DATAgeneralElectrical ch
Page 457 and 458: MECHANICAL DATAceramic packages -ce
Page 459 and 460: MECHANICAL DATAplastic packages (N
Page 461 and 462: MECHANICAL DATAceramic chip carrier
Page 463 and 464: Texas InstrumentsSemiconductor Tech
Page 465 and 466: TI Sales Offices TI DistributorsALA
Page 468:
Printed in U.S.A.•TEXASINSTRUMENT
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