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Applications BriefTMS4500A/8088 INTERFACEThis application brief presents a circuit configuration which interfaces the 8088 microprocessor to dynamic RAMmemory via the TMS4500A-15 dynamic RAM controller. The memory array is 32K bytes deep and featuresthe TMS4416 16K X 4 dynamic RAM. The TMS4416 was used for its modularity advantage over X 1 DRAMs.Figure 1 shows the schematic diagram of the circuit while Figure 2 depicts the timing diagram of a write accessfollowed by a refresh followed by a read access grant memory cycle. The 8088 and TMS4500A both operateat 5 MHz requiring no wait states on normal memory accesses. The TMS4500A clock is shifted by one 15 MHzclock cycle via a 74S74 to ensure the proper ALE low to ClK low relationship to the TMS4500A. In order tocover the important TMS4500A interface requirements, the six-point design criteria will be used as presentedin the "TMS4500A Dynamic RAM Controller Users Manual."1 . Refresh TimeThe TMS4500A is configured for maximum division of the clock without inserting wait states by strapping TWST,FS1, and FSO as follows: TWST = 0, FS1 = 1 and FSO = 1.This strap configuration divides the clock by 61 to yield a refresh rate of 3.123 ms (see TMS4500A Spec.).2. Memory Pre charge timeThe memory precharge time must be calculated for consecutive access, refresh, and access grant cycles toensure that the minimum RAS precharge time is satisfied.a. Access CyclesThe precharge time for access cycles is given by:wheretRPTClClTClCl + TClCH - TClRH - tACH-REH - tt(REH) + TCHll+ tAEl-REl *RAS precharge timeClK cycle periodc:o'';::COE...o'too..5(I)c:o'';::CO,~Q.c.•