1 - Al Kossow's Bitsavers

whereta(C)tp(BFR)(-103 + tc2 - tp(BFR)) nsBuffer propagation delay, input to output of the ALE buffer. (MAX, Spec.)Using the worst case CAs access time for TMS4164-15 DRAMs (ta(c) = 100 ns), the maximum allowable propagationdelay for the buffer can be determined:tp(BFR)(-103 + tc2 + talc)) ns(-103 + 333 -100) ns130 nsThis value must be greater than the maximum propagation delay for the ALE buffer.The specifications for the high-speed version will be evaluated next. In this version, ALE is extended to meet the RAS prechargerequirement for -15 devices. This also gives sufficient address setup time to use the 74LS61 0 memory mapper. The memorymapper performs essentially the same function as the bipolar RAM array in the previous example, but incorporates the controlsignals that are necessary on-chip. For more information regarding the 74LS610, refer to TI Application Brief entitled"Memory Mapping Using the SN54/74LS610 Thru SN54/74LS613 Memory Mapper." For the following example, assumethat the TMS99000 has an input CLKIN frequency of 20 MHz (CLKOUT = 5 MHz).1. Refresh TimeFrom Table 1 of the TMS4500A data sheet, the strap selection should be FSO = 0, FS1 = TWST = 1. This will yielda refresh rate of 66 MHz and each refresh cycle will take 4 clock cycles. Also, the TMS4500A will insert one wait stateon each access cycle. As was mentioned earlier, the external logic will insert two wait states on each access cycle withthe assistance of the RDY signal from the TMS4500A.2. Memory Precharge Time (RAS precharge)l>~"2-c;'Dl...O·::len:;-......03Dl...•o·:;,a. Access CyclesThe precharge time on access cycles is given by:b.c.wherethustc2~p('LS04)t p('S74)tRPAccess Grant CyclesthusRefresh Cyclesthustc2 + tp('LS04) + t p('S74) + tAEL-REL * - td7 - tACH-REH - tt(REH)200 nsPropagation delay, input to output (MIN, 74LS04 Spec.)Propagation delay, clock to Q output (MIN, 74S74 Spec.)(200 + 6 + 4 + 36 - 30 - 40 - 20)ns156 ns RAS precharge time .tc2 = tCH-REL * - tCH-RRH - tt(REH)(200 + 63 - 45 - 20) ns198 ns RAS precharge time.1 .5[tc2) + tCH-RRL * - td7 - tACH-REH - tt(REH)[1.5(200) + 54 - 30 - 40 - 20) ns264 ns RAS precharge time.3. ALE to eLK RelationshipAs mentioned previously, a schottky flip-flop and low-power schottky inverter are used to clock ALE so that a minimumof 10 ns delay is guaranteed from CLK low to ALE low.• Multiply the specified maximum value by 0.9.9-60