1 - Al Kossow's Bitsavers

thust p('S373)tp('S189)tRAV-MAVtsu(AR)Propagation delay, data input to output (MAX, 74S373 Spec.)Propagation delay, address input to output (MAX, 74S189 Spec.)Time delay, row address valid to memory address valid (MAX, 4500A-20 Spec.)[(333/4 + 10) + 36 - 15 - 13 - 35 - 55) ns16 ns row address setup time for the DRAMs.The row address hold time is guaranteed by the TMS4500A for -12, -15, and - 20 speed range devices.5. Data Valid to Write EnableSince CAS is initiated by the write enable signal, all write cycles are necessarily early write cycles. Therefore, we will calculatethe setup time for data valid to CAS starting low which is given by:wherethustsu(D)tsu(D)tAEL-CELtd9td1td8tsu(D)tAEL-CEL + td9 - td1 - td8Setup time, write data valid to CAS starting lowTime delay, ALE low to CAS starting low (MIN, 4500A-20 Spec.)Delay to WE from reference line (MAX, 99000 Spec. *)Delay to ALATCH low from reference line (MAX, 99000 Spec.)Delay from ALATCH low to valid write data (MAX, 99000 Spec.)[75 + (333/4 + -18) - (333/4 + 20) - 35) ns38 ns setup time from data valid to CAS starting low.6. Read Access TimeThe maximum access time allowable from CAS to data valid on memory read cycles is given by:talC)tc2 - tc2/4 - td1 - tAEL-CEL - tsu2where talC)tc2tc2/4td1tAEL-CELtt(CEL)tsu2Access time from CAS to data validCLKOUT periodDelay from CLKOUT falling to reference line (99000 Spec.)Delay from reference line to ALATCH low (MAX, 99000 Spec.)Time delay, ALE low to CAS starting low (MAX, 4500A-20 Spec.)CAS fall time (MAX, 4500A-20 Spec.)Data setup time (to CLKOUT falling) (MIN, 99000 Spec.)thus talC) [333 - 333/4 - (333/4 + 20) + 20) - 200 - 25 - 25) nsco.~COE....-o.5tJ)co.~CO.~Q.c.~'. ... = . -1~3 ~s. . . d b d •Now that the SIX specifications on the deSign criteria checklist have been examined, the values obtalne can e compareto those required for the TMS4164. This comparison shows that three criteria constrain design and memory selection. Thesecriteria are RAS precharge, CS valid to ALE starting low, and read access from CAS. The RAS precharge time of 123 nsmeans that only -20, -15, or -12 speed range devices may be used. Next, 3.2 ns of delay must be added to the ALEsignal to ensure that CS is valid 10 ns before ALE starts low. This delay is achieved by inserting a buffer between ALATCHand ALE. Finally, a negative access time from CAS requires that a wait state must be inserted on each memory accesscycle. By adding one CLKOUT period (set TWST = 1, FSO = FS 1 = 0) to the calculated memory access requirement,the read access cycle time (from CAS) with one wait state inserted is given by:• Multiply the specified maximum value by 0.9.9-59