1 - Al Kossow's Bitsavers

. Access Grant CyclesThe precharge time for access grant cycles is given by:wherethustRPtCH-REltCH-RRHtRPtc2 + tCH-REl * - tCH-RRH - tt(REH)Time delay, ClK high to access RAS starting low (MAX, 4500A-20 Spec. *)Time delay, ClK high to refresh RAS starting high (MAX, 4500A-20 Spec.)(333 + 63 - 45 - 20) ns = 331 ns RAS precharge timec. Refresh CyclesThe precharge time for refresh cycles is given by:wherethustRPtCH-RRltRP1.5 (tc2) + tCH-RRl * - td7 - tACH-REH - tt(REH)Time delay, ClK high to refresh RAS starting low (MAX, 4500A-20 Spec. *)[1.5(333) + 54 - 30 - 40 - 20] ns = 464 ns RAS precharge time3. ALE to elK RelationshipALE low transition must not occur within 10 ns of the ClK low transition. Since the TMS99000 strobes ALATCH Iowanthe rising CLKOUT edge, this criterion is satisfied.4. Row Address Setup and Hold Timesl>'C"2-C;"Q)r+o·:;:,en;--h0~3o·Q)r+•:;:,The row address, column address, REN 1 and CS inputs must all be set up and stable no later than 10 ns prior to the fallingedge of ALE. The latest of these signals will be CS which must propagate through all of the memory decode logic. Therow address setup time for the 4500A then is given by:wherethustAV-AEltAV-AEltd2t w H3td3t p('S373)t p('S189)t p('S138)tAV-AELtd2 * + twH3 - td3 - t p('S373) - t p('S189) - t p('S138)Setup time, row, column, REN1, CS valid to ALE starting low (MIN, 4500A-20Spec.)Delay to ALATCH high from reference line (MAX, 99000 Spec. *)ALATCH pulse width high (MIN, 99000 Spec.)Delay to address valid from reference line (MAX, 99000 Spec.)Propagation delay, data input to output (MAX, 74S373 Spec.)Propagation delay, address input to output (MAX, 74S189 Spec.)Propagation delay, select input to output (MAX, 74S138 Spec.)[13.5 + (333/4 - 15) - 15 - 13 - 35 - 12] ns6.8 ns setup time from CS to ALE starting low.The setup time from row address valid (at the DRAMs) to RAS starting low must also be considered. This is given by:wheretsu(AR)t§u(AR)td1tAEL-REltd3td1 + tAEl-REl * - td3 - t p('S373) - t p('S189) - tRAV-MAVSetup time, row address valid to RAS starting lowDelay to AlATCH low from reference line (MIN, 99000 Spec.)Time delay, ALE low to RAS starting low (MAX, 4500A-20 Spec. *)Delay to address valid from reference line (MAX, 99000 Spec.)• Multiply the specified maximum value by 0.9.9-58