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Applications BriefTMS4500A DRAM CONTROLLER CONFIGURED FOR THETMS99000 SERIES 16-BIT MICROPROCESSORSThe TMS4500A dynamic RAM controller can be used in various configurations with TMS99000 series 16-bitmicroprocessors.' A medium-speed version and its timing diagram are shown in Figures 1 and 2, respectively.A high-speed version and its timing diagram are shown in Figures 3 and 4, respectively. Two memory configurationsare also shown: a bulk memory configuration and a modular array. The bulk memory configuration uses32 TMS4164 dynamic RAMs arranged as 128K of 16-bit words (see Figure 5). The modular memory array iscomprised of 16 TMS4416 16K X 4 dynamic RAMs arranged as 64K of 16-bit words (see Figure 6). The modulararray can be reduced in 16K word increments to a system that is 16K words deep for less memory-intensiveapplications. In addition, signals have also been provided to increase the memory depth to 128K words. In theparagraphs that follow, a description of both speed versions will precede a six-point analysis of the design criteriapresented in the "TMS4500A Dynamic RAM Controller Users Manual." Both versions will be analyzed to ensurea proper match of timing signals between processor and memory.The 15 address lines (AO-A 14) and Pm are latched by two 74S373 8-bit data la'tches as shown in Figure 1.2Latched addresses A 1-A4 are used to address three 16 X 4 bipolar RAMs in order to generate eight higher-ordermemory address lines. These RAMs are used as a memory mapping function to increase the memory space ofthe TMS99000. Four of the higher order address lines are decoded into chip selects for all memory-mappeddevices. On powerup and reset, the TMS99000 fetches the reset trap vector located at memory address OOOOH.Since PSEL is forced high for this fetch, the three memory-map RAMs are deselected, allowing their outputsto be pulled high by the 10k pullup resistors. This deselects the memory decoder and enables EPROM. Part ofthe reset service routine residing in EPROM should include instructions to load the memory mapper. The memorymapper is addressed using the 1/0 interface of the TMS99000 that has both serial and parallel bit manipulationcapabilities.Address lines A 1-A4 are used to address the memory-map RAMs. AO is set to a one for parallel 1/0 transfers(see TMS99000 Data Book). Additional 1/0 ports could be addressed by using the Y6 output (1/0 transfer) ofthe bus status decoder to enable an 110 decoder connected to the address latch outputs. Because of the largememory address space provided by the memory mapper, however, it was felt that all additional 1/0 ports couldbe memory-mapped.co.~COE...... o.5U)co.~CO.~Q.Q.~1 All references to the TMS99000 apply to both the TMS99105A and TMS99110A microprocessors.2 It should be noted that the TMS99000 uses the convention that AO to A 14 represent the most to least significant address bits. respectively.9-51