1 - Al Kossow's Bitsavers

Figures 6 and 7 show how the edge timings of ALE and ACX described in the previous examples affect the RAS and CAStimings on access grant cycles. An access grant cycle occurs when ALE goes low during a refresh cycle. In this case thetiming of ALE low to ACX low determines the timing of RAS and CAS low with respect to ClK. If ACX falls more than20 ns after ALE during a refresh cycle, the TMS4500A will follow the timing shown in Figure 6. If ACX falls prior to orless than 2 ns after ALE during a refresh cycle, the TMS4500A will follow the timing shown in Figure 7. The differencebetween the two timing diagrams is the CAS timing with respect to ClK. On access grant cycles, the falling edge of ALEcauses the ROY signal to go low; ROY low is generally used to hold off the processor until the refresh cycle is complete.The refresh timings of RAS, CAS, and MAO-MA 7 are identical to the fifth example with respect to ClK edges A, B, C,and O. ClK edge E in Figures 6 and 7 terminates the refresh cycle and initiates the access grant cycle by bringing the ROYsignal high and the RAS signallow. 1 In Figure 6 (ACX falling more than 20 ns after ALE), the CAS signal is timed fromthe subsequent falling edge of ClK after the access grant cycle is initiated (ClK F) and will go low tCl-CEl later. In Figure 7(ACX falling prior to or less than 2 ns after ALE), the CAS signal is timed from the rising edge of ClK that initiated theaccess grant cycle (ClK E) and will go low tCH-CEl later. This diagram shows that CAS will fall approximately one-halfClK cycle earlier in Figure 7 than CAS in Figure 6; this timing arrangement decreases the access time after refresh. In bothof these access grant examples, the cycle is terminated by the low-to-high transition of ALE and ACx as described above.ClKALEACXRASMAO-MA7CASREFREQROYc00';:'CO.. E0'I-.5enc00';:'CO09C.~