1 - Al Kossow's Bitsavers

ALEACXRASMAO-MA7CASFIGURE 1 -ALE LEADING ACXALEACXRASMAO-MA7CASFIGURE 2- ALE OVERLAPPING ACXThe next example shows ACX prior to or coincident with ALE (see Figure 3). When ACX falls prior to or coincident withALE, the falling edges of RAS, CAS, and the switching of MAO-MA 7 are controlled by the falling edge of ALE. In this case,the TMS4500A provides several of the memory timing signals. First, the row address hold time (RAS low to MAO-MA7switching) is guaranteed to be a minimum of 30 ns (tREL-MAX); this value satisfies the row address hold times (tRAH)of TMS4164/TMS4416 (-15 and -20) DRAMs. Secondly, ALE low to CAS low (tAEL-CELI is within a guaranteed maximum.The rising edges of ALE and ACX have the same functions as described in the second example. In many applications, ALEand ACX can be tied together to take advantage of this "automatic timing feature" of the TMS4500A.Figure 4 illustrates the case where ACX overlaps ALE. In this case, the falling edges of ALE and ACX have the same functionas described in the third example: that is, ALE controlling RAS, CAS, and the switching of MAO-MA 7. The rising edgesof ALE and ACX have the same function as described in the first example: that is, ALE controlling RAS and the switchingof MAO-MA 7 while ACX controls CAS.9-46