1 - Al Kossow's Bitsavers

TMS4500AALE AND ACX TIMINGThis application brief describes the timing diagrams for several configurations that can be achieved with theTMS4500A by controlling ALE and ACX. (ACX refers to either ACR or ACW.) Example timing diagrams are giventhat illustrate the pertinent edge timings of ALE and ACX and their impact on system timing requirements.The timing diagram given in Figure 1 shows ALE leading ACX. The falling edge of ALE latches the CS, REN1,RAO-RA7, and CAO-CA7 inputs (not shown in the diagram); if CS is valid, RAS will go low tAEL-REL after ALElow. ACX going low has two functions: the MAO-MA7 outputs are switched from the row addresses to thecolumn addresses, and CAS will go low when these addresses become valid. The access time of the TMS4500A(ALE low to CAS low) is specified as tAEL-CEL providing ACX goes low less than tAEL-CEL - tACL-CEL afterALE. If this condition is not met then the access time increases and CAS low is measured from the low-goingedge of ACX instead of ALE (tACL-CELl. The rising edge of ALE brings RAS high and causes the inputs at RAO-RA7to be output as addresses on MAO-MA 7. (Input latches for RAO-RA 7 are transparent latches.) The rising edgeof ACX brings CAS high and terminates the memory access cycle. The edge placements of ALE and ACX canvary from this example giving rise to RAS and CAS timings not explicitly shown in the MOS Memory Data Bookas explained below.Figure 2 illustrates the case where ALE overlaps ACX. In this case, the falling edges of ALE and ACX have thesame function as explained in the first example although the rising edges take on a little different function. Referringto. Figure 2, it can be seen that the rising edge of RAS, CAS, and the switching of MAO-MA 7 are controlledby the rising edge of ACX. The rising edge of ALE has no control in this example. Because ACX brings RAShigh, the precharge time (tRP) required by DRAMs is initiated from the rising edge of ACX and terminated bythe subsequent falling edge of ALE. This timing can be helpful in a system that cannot meet RAS prechargetime initiated from ALE.co'';:;COE ..o-.5U)co'';:;CO,~Q.c.