1 - Al Kossow's Bitsavers

TMS4500A BLOCKS 1 AND 2 BLOCKS 3 AND 4FIGURE 3 -64K X 16 CONFIGURATIONAnother example takes advantage of having a 32-bit word available but only an 8-bit data bus. To take advantage of this, a74LS139 selects the WR and RD signals and 00-07 of each block are tied together to form an 8-bit bus (See Figure 4). Awrite cycle enables 1 G allowing the 1 A and 1 B signals to select the block to be written to. A read cycle enables 2G allowingthe 2A and 2B signals to select which block will be read. On a read cycle, the 2A and 2B signals can be sequenced, causingsuccessive activation of the RD lines to rapidly access all 32 bits over the 8-bit bus (See Figure 5). This configuration makesfull use of the output enable (