1 - Al Kossow's Bitsavers

The TMS4416/TMS4500A board is arranged as two rows of 8 devices (see Figure 2). Row 0 and Row 1 are selected bythe RASO and RAS1 sign,als, respectively. The board is then subdivided into four blocks of 32K bytes that are controlledby the WR1-WR4 and RD1-RD4 signals. The strapping of WR1-WR4 and RD1-RD4 allows the board to be configured as32K X 32 bits, 64K X 16 bits, or 128K X 8 bits. Table 1 shows the typical strapping needed for the various word widths.Several examples of how the WR and RD signals can be used will show the versatility of the TMS4416/TMS4500A board.BLOCK 0 BLOCK 1 BLOCK 2BLOCK 3TMS4500AUlTMS4416I I-' IRASO- I II I III IIU2 U3 U4 U5 U6 U7I I I--RASl-I I II I II I I- Ul0 Ull U12 U13 U14 U151 I' , I I 1 IWR2WR3U8U16IIIII •iIIIIU9U171 IWR4 RD4ROW 0ROW 1FIGURE 2 -TMS4416/TMS4500A BOARD lAYOUTTABLE 1 - READ AND WRITE SIGNAL STRAPPING CONFIGURATIONCONFIGURATION128K X 864K X 16SIGNAL STRAPPINGSWR1 = WR1, 'S"WR2 = WR2, 'S"WR3 = WR3. SWR4 = WR4SRD1 = RD1, SRD2 = RD2, SRi5'3 = RD3, SRD4 = RD4SWRl = WR1 = WR2. SWR2 = WR3 = WR4SRD1 = RD1 = RD2. SRD2 = RD3 = RD4TYPE OF CONTROLSeparate ControlCombined Pairs•NOTES:32K X 321. WRX = Write signal for any block.2. RDX = Read signal for any block.3, SWRX = User supplied system write signal.4. SRDX = User supplied system read signal."SWR1 = WR1 = WR2 =wib = WR4SRi5'1 = Ro1 = RD2 = RD3 = Ro4All CombinedThe REN1 input on the TMS4500A selects which row of devices is selected by controlling the RAS (Row Address Strobe)signals (REN1 low selects RASO, REN1 high selects RAS1). When a row of memory is accessed (RASO low or RAS1 lowl. allthe devices in that row are active which allows the user to manipulate each half-block within a row separately or collectively.As an example, strapping WR1-WR4 and RD1-RD4 for 64K X 16 operation as shown in Table 1 combines the 32-bit databus to form two 16-bit data busses that can be used in 16-bit systems as shown in Figure 3. The I/O function is controlled bythe combination of WR1-WR2, RD1-RD2 (Blocks 1 and 2) and WR3-WR4, RD3-RD4 (Blocks 3 and 4). It is then possible toread and/or write to each block by appropriate control of the WR and RD signals.9-40