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DOTCLOCKCLOCK ACLOCK C2 xWCLKRAS (ALE)MUXCASGLOAD--------------------------------------~--~Figure 2. Display And Refresh Cycle Timing»"C"2-(;'Q)...0'~en...~-t\o3Q)...•0'~2xWClKMUXA C o E GI I I I IFigure 3. RMW Cycle Timing9-34
The video output circuitry closely resembles that providedin the 7220 Design Manual. The major difference beingthe manner in which the 74S299 load pulse is generated.It was decided to use the ripple carry out of a 74S163 insteadof gating the clock outputs together. The CAS signalenables the 74S163 and six dot clocks later (edge F) the ripplecarry out will go high (see Figure 2) providing a videoload pulse at the end of the display cycle (edge G). Thisreduces hardware and provides an easy means for varyingthe position of the load pulse within the memory cycle ifnecessary. Some applications may require the video loadpulse to occur earlier in the display cycle which is accomplishedby changing the input strapping of the 74S163.A video load pulse will occur on every memory access;however, on refresh and RMW cycles, the display is blankedpreventing any disturbance of the display. Since the firstword of video information on each horizontal scan is not validuntil the end of the first display cycle, video unblanking mustbe delayed for one display cycle. This is accomplished byclocking the 7220 BLANK signal with the NAND result ofthe inverted dot clock and ripple carry out through a 74S74.The video is then synchronized with the dot clock and outputto the monitor. A 74LS123 is used to provide the properhorizontal and vertical drive signals to the monitor. <strong>Al</strong>thoughthe 7220 can be programmed for the horizontal sync widthand the vertical sync width, some monitors require long drivetimes that can only be implemented with external logic.Providing the correct video information to the monitorrequires several calculations to determine the necessaryparameters that must be supplied to the 7220 upon initialization.The 7220 Design Manual goes through detailed calculationsfor determining these parameters when the designer isin the specification stage of a design. For this design themonitor specifications and dot clock rate were assumed andthe other parameters derived accordingly. The necessaryspecifications and calculations are given below.Horizontal frequency = 15.75 kHzVertical frequency = 60 HzHorizontal blanking = 11 p.s nominalVertical blanking = 900 p.s nominalDot clock = 11.34 MHz2 x WCLK = 1.42 MHz (Dot clocle/8)Word time = 1.41 p.s [2(1/2 xWCLK)1Line time = 63.5 p.s (lIHorizontal frequency)Pixel time = 88.18 ns (lIDot clock)From the line time and pixel time, the total number ofpixels per horizontal scan can be calculated.Pixels= tLINE/tPIXEL= 63.5 Its/88.18 ns= 720The total number of words per horizontal scan is givenby:WT = Pixels/16= 720116= 45(Since the 7220 uses a 16-bit word)The total word count is then divided between displayedwords and blanked words. For the monitor used, the onlyrestriction on the horizontal parameters is that the sum ofhorizontal front porch, back porch and sync be approximatelyequal to the nominal horizontal blanking time (11 its). Thehorizontal drive to the monitor is set by the 74LS123. Ahorizontal resolution of 512 pixels would require 32 displaywords and leave 13 words for horizontal blanking. SettingHorizontal Back Porch (HBP) = 5, Horizontal Front Porch(HFP) = 5, and Horizontal Sync (HS) = 3 meets all 7220constraints except for light pen use (requires HFP > 6words), and also satisfies the monitor horizontal blankingtime.Horizontal blank13 x 1.41 itS18.33 itSCalculations to determine the vertical blanking parametermust also be made.Total number of lines = (l/vertical frequency)/line time= (1160)/63.5 its= 262.3 (use 263)The total number of lines is also broken into active andblanked lines. In this application it was desired to neglectaspect ratios and display as much on the screen as possibleand stay within the monitor specifications. For this reason,it was decided to display 240 lines and blank 23 lines for512 x 240 noninterlaced and 512 x 480 interlaced displayresolution. Again the vertical drive is set by a 74LS123 andthere are no restrictions placed on the breakdown of the verticalblank parameters by the monitor or the 7220, allowingrandom division of the 23 blanked lines. The followingparameters were chosen: Vertical Back Porch (VBP) = 3lines, Vertical Front Porch (VFP) = 2 lines, and VerticalSync (VS) = 18 lines.Vertical blank = Blanked lines x one line time= 23 x63.5 itS= 1.46 msSeveral points of interest relating to the choice of thehorizontal and vertical parameters are given in the followingparagraphs.A. Dynamic RAM refresh, if necessary, is only done duringhorizontal and vertical sync which needs to be longenough to allow sufficient memory refresh.co'.;ICO... E.... o.Eenco'.;ICO,~Q.c.«9-35
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SMYOOO2.,MOS MemoryData Book1984II
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ALPHANUMERIC INDEX TO DATA SHEETSSM
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TABLE OF CONTENTSALPHANUMERIC INDEX
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MOSLSIRAMs, ROMs, EPROMsSELECTION G
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If you want to give it a try for yo
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INTERCHANGEABILITY GUIDEPART 1 -ALT
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INTERCHANGEABILITY GUIDEFUJITSUMB 8
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INTERCHANGEABILITY GUIDEMOTOROLAMCM
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INTERCHANGEABILITY GUIDETOSHIBATMM
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INTERCHANGEABILITY GUIDESTATIC RAMS
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Alphanumeric Index, Table of Conten
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GLOSSARY fTIMING CONVENTIONS/DATA S
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GLOSSARY/TIMING CONVENTIONS/DATA SH
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GLOSSARY!TIMING CONVENTIONS/DATA SH
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MOSLSITMS411616,384-811 DYNAMIC RAN
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TMS411616,384·811 DYNAMIC RANDOM·
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1MS411616,384-811 DYNAMIC RANDOM-AC
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TMS411616.384·81T DYNAMIC RANDOM·
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zIiADDRESSES~!.....RASCASwDO"*. i,*
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TMS411616,384-81T DYNAMIC RANDOM-AC
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MOSLSITMS416165,536-81T MULTIPORT M
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TMS416165,536-811 MULTIPORT MEMORYf
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TMS416165,536-BIT MULTIPORT MEMORYs
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TMS416165,536-0IT MULTIPORT MEMORYc
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TMS416165,536·BIT MUL TIPORT MEMOR
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TMS416165,536 o BIT MUL TIPORT MEMO
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TMS416165,536·811 MULTIPORT MEMORY
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zI[~~~co,.. twiRL) _,RAS:::~ SI l L
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TMS416165,536·BIT MULTIPORT MEMORY
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~ ___TMS416165.536-BIT MUL TIPORT M
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0>~a~~i'i_';:;Z~~~d~c:::• s:~lTl~
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TMS416165,536-8IT MULTIPORT MEMORY1
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MOSLSITMS4164, SMJ416465,536-8IT DY
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TMS4164, SMJ416465,536-811. DYNAMIC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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SMJ416465,536-81T DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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TMS4164, SMJ416465,536·81T DYNAMIC
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TMS4164, SMJ416465,536·8IT DYNAMIC
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z~~gz~.J:>.c1J
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Z~d~~~~0,'...."CIIICCCD:3of. twIRL)
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MOSLSITMS4256. TMS4257262.144·8IT
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TMS4256, TMS4257262,144·8IT DYNAMI
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TMS4256, TMS4257262,144-8IT DYNAMIC
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TMS4257262.144·8IT DYNAMIC RANDOM
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TMS4256, TMS4257262,144·BIT DYNAMI
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TMS4257262,144·81T DYNAMIC RANDOM
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Z~d~~~~.!..JcoNOTE:'CIIICO(1),- twI
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i:Z~d~~z~+:>0Co ......"CCICCCD:3og.
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MOSLSITMS4416. SMJ441616.384·WORD
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TMS4416, SMJ441616,384·WORD BY 4·
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TMS441616,384-WORD BY 4-BI1 DYNAMIC
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TMS441616,384-WORD BY 4-BIT DYNAMIC
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SMJ441616,384·WORD BY 4·BIT DYNAM
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SMJ441616,384-WORD BY 4-B11 DYNAMIC
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1MS4416, SMJ441616,384·WORD BY 4·
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TMS4416, SMJ441616,384·WORD BY 4·
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z~~~z@towRAs-{rCASAO·A7wDQG:::'.!A
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1:'QltC(()3oc..(()C3~~n_:::Z~~~;;;
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MOSLSITMS446465,536-WORD BY 4-BIT D
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TMS446465,536-WORD 8Y 4-81T DYNAMIC
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TMS446465,536·WORD BY 4·BIT DYNAM
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1MS446465,536·WORD BY 4·B11 DYNAM
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TMS446465,536·WORD BY 4·BIT DYNAM
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RASCAS----{! '.,ReIVIH i~VIL I tRLC
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~~~n_;;;z~~. ~~tTlg ;O~d ;;;t::=z~@
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~Z~~iZ~tw '"[:;-~~~~~:TCDCO ".;:r0~
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MEMORY SUPPORTLSITMS4500ADYNAMIC RA
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TMS4500ADYNAMIC RAM CONTROLLERpin d
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TMS4500ADYNAMIC RAM CONTROLLERarbit
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TMS4500ADYNAMIC RAM CONTROLLERswitc
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TMS4500ADYNAMIC RAM CONTROLLERacces
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TMS4500ADYNAMIC RAM CONTROLLERoutpu
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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•••••MOSLSI65,536 X 4 Org
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TM4164EC465,536 BY 4·BIT DYNAMIC R
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MOSLSITM4164EL965,536 BY 9·BIT DYN
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TM4164EL965,536 BY 9-BIT DYNAMIC RA
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••••••••0MOSLSI65,5
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TM4164FL865,536 BY 8·BIT DYNAMIC R
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MOSLSITMS2516. SMJ251616.384-BIT ER
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TMS2516, SMJ251616,384-BIT ERASABLE
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TMS251616,384·BIT ERASABLE PROGRAM
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SMJ251616,384-BIT ERASABLE PROGRAMM
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o 441MS2516, SMJ251616,384·B11 ERA
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MOSLSITMS2532, SMJ253232,768·BIT E
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TMS253232,768-BI1 ERASABLE PROGRAMM
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MOSLSITMS2564, SMJ256465,536-BIT ER
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TMS256465,536-BIT ERASABLE PROGRAMM
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TMS2564 r SMJ256465 r536-BIT ERASAB
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MOSLSITMS2708, TMS27L08, SMJ2708, S
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TMS270B, TMS27LOBSMJ270B, SMJ27LOB1
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TMS2708. TMS27L081024·WORD BY 8·B
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SMJ2708, SMJ27L081024·WORD BY 8·B
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TMS2708, TMS27L08SMJ2708, SMJ27L081
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MOSLSITMS27162048·WORD BY 8·BIT E
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TMS27162048·WORD BY 8·BIT ERASABL
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TMS27162048-WORD BY 8-BIT ERASABLEP
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TMS2732A32,76B-BIT ERASABLE PROGRAM
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TMS2732A32,768-BIT ERASABLE PROGRAM
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TMS2732A32,768·BIT ERASABLE PROGRA
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MOSLSITMS276465,536-BI1 ERASABLE PR
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TMS276465,536·BIT ERASABLE PROGRAM
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MOSLSITMS27128131,072·BIT ERASABLE
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TMS27128131,072·BI1 ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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MOSLSITMS46648192·WORD BY 8·BIT R
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TMS46648192·WORD BY 8·BIT READ·O
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MOSLSITMS47324096~WORD BY B·BIT RE
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MOSLSITMS47648192·WORD BY 8·BIT R
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MOSLSI, TMS49648192·WORD BY 8·BIT
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MOSLSITMS4712816,384·WORD BY 8·BI
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TMS4712816,384·WORD BY 8·BIT READ
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TMS4712816,384-WORD BY 8-BIT READ-O
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MOSLSITMS4725632.768·WORD BY 8·BI
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TMS4725632.768·WORD BY 8·BIT READ
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MOSLSITMS2114, TMS2114L1024·WORD B
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TMS2114, TMS2114L1024·WDRD BY 4·B
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TMS2114. TMS2114L1024·WORD BV 4·B
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ADVANCED MEMORYDEVELOPMENT•Fast A
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TMS2150CACHE ADDRESS COMPARATORabso
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TMS2150CACHE ADDRESS COMPARATORPARA
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MOSLSITMS40162048·WORD BY 8·BIT S
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TMS4016204H-WORD BY H-BIT STATIC RA
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TMS40162048-WDRD BY 8-BIT STATIC RA
Page 333 and 334: MOSLSITMS4044, TMS40L444096-WORD BY
Page 335 and 336: TMS4044, TMS40L444096·WORD BY 1·B
Page 337 and 338: TMS4044, TMS40L444096·WORD BY l·B
Page 339 and 340: MILITARYCMOSLSISMJ55172048-WORD BY
Page 341 and 342: SMJ5517204a·WORD BY a·BIT STATIC
Page 343 and 344: SMJ55172048·WORD BY 8·BIT STATIC
Page 345 and 346: SMJ55172048-WDRD BY 8-BIT STATIC RA
Page 347 and 348: SMJ5517204B·WORD BY B·BIT STATIC
Page 349: Alphanumeric Index, Table of Conten
Page 352 and 353: However, the TMS 4164 provides the
Page 354 and 355: EXPANSION OF 3242 FOR 256-CYCLE REF
Page 356 and 357: •9-6
Page 358 and 359: PAD OPENINGIN OVERCOATPADMETALPADME
Page 360 and 361: Figure 5 shows how the driver outpu
Page 362 and 363: cpI UO,leWJOJUI suo'le:>!ldd"f\)W(3
Page 364 and 365: The falling edge of RAS causes R 1
Page 366 and 367: ~--------::~~:~:~~~:--------~~7,34(
Page 368 and 369: J-Lead AdvantageTexas Instruments P
Page 370 and 371: Surface Mount Component Availabilit
Page 372 and 373: fiSECONDARYVAPOR(VAPOR BLANKET)..Fi
Page 374 and 375: l>'C'2.ri'Q),..o·:::Jen5'....... o
Page 376 and 377: l>"C'2..(i"Dl...0":=(I)5"....o...3D
Page 378 and 379: An external refresh counter has bee
Page 380 and 381: l>'C'CC:)"Q).-+o·::::sen:ro ... ""
Page 382 and 383: uo!~ew"oJul suo!~ea!ldd"CD .,.., w7
Page 386 and 387: B. If dynamic RAM refresh is enable
Page 388 and 389: •9-38
Page 390 and 391: The TMS4416/TMS4500A board is arran
Page 392 and 393: RAS ~CAS \ I2AI \ I '-2BI '-iiD1Ro2
Page 394 and 395: 9-44
Page 396 and 397: ALEACXRASMAO-MA7CASFIGURE 1 -ALE LE
Page 398 and 399: The ALE high to ClK low time is giv
Page 400 and 401: ClKALEACXRASMAO-MA7CASREFREQROY•
Page 402 and 403: CDinN~1~12 MHzClKINClKOUTWE/iOclKRD
Page 404 and 405: UO!leWJOJUI SUOlle:ludd"com~'~,i'74
Page 406 and 407: coen(J)CLOCKWRITEREADROYALEA14-A5MS
Page 408 and 409: . Access Grant CyclesThe precharge
Page 410 and 411: whereta(C)tp(BFR)(-103 + tc2 - tp(B
Page 412 and 413: •9-62
Page 414 and 415: tt(REH)TCHLLtAEL-RELRAS rise time (
Page 416 and 417: . Refresh CyclesOn refresh cycles t
Page 418 and 419: wherethus,fCLKfCLKtCACfCLK[1/2 (tCA
Page 420 and 421: R/W approach does a normal read-mod
Page 422 and 423: II(0~""6 MHzI UO!leWJO,ulSUo!le:l!l
Page 424 and 425: ClKAlE.ACR\ ,----\,\ ,----R/W\ ,---
Page 426 and 427: 4. Row address setup and hold timeT
Page 428 and 429: CLKrWRITE -------I.~ ..~---REFRESH-
Page 430 and 431: The read access time on access gran
Page 432 and 433: implementations in order to relieve
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"C'2..c:rm...o·j(I)....5'o3...mo·
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RELATIVE MEMORY SIZEARCHIVAL STORAG
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increments till satisfied. This pro
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In the example shown in Figure 5, t
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»'C"E..crQ)r+0':::Jtil:;-....o...3
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•9-94
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184LOGIC SYMBOLS1. INTRODUCTIONEXPl
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LOGIC SYMBOLS4.DIAGRAMATIC SUMMARYI
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lOGIC SYMBOLSWhen RAS goes low, it
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MECHANICAL DATAgeneralElectrical ch
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MECHANICAL DATAceramic packages -ce
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MECHANICAL DATAplastic packages (N
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MECHANICAL DATAceramic chip carrier
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Texas InstrumentsSemiconductor Tech
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TI Sales Offices TI DistributorsALA
Page 468:
Printed in U.S.A.•TEXASINSTRUMENT
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