1 - Al Kossow's Bitsavers

allows the use of multiple rows of memory since both CASand G have to be low for the TMS4416 outputs to be active(see TMS4416 operation, 1982 MOS Memory Data Book).The cycle is terminated by the rising edge of ALE (edge G).On RMW cycles, the 7220 uses the DBIN signal to gatedata from the memory onto the bus signifying the read operation.The rising edge of DBIN is then used to disable theG signal terminating the read portion of the cycle (seeFigure 3). The 7220 does not provide a separate write signalso the memory control circuit must use the presence of DB INto generate the write signal. This is accomplished by shiftingDBIN two clock C cycles (edge E) with two 74LS74s.Again the rising edge of ALE terminates the memory cycle(edge G).The 7220 runs at a relatively slow clock speed (1.4 MHz)in this design allowing the use of Low Power Schottky componentsfor most of the memory control circuitry. Thenecessary memory calculations given below show the actualmargins and also provide an easy means for determining themaximum speed of the design with Schottky components.The critical memory timings to be covered are: RASprecharge, row address setup and hold, CAS access, datavalid to write enable time and refresh interval.RAS Precharge TimetRP = tRW - tS(74LS08)where: tRW = ALE width (MIN, 7220 Spec.)ts = Skew between tpHL and tpLH, 74LS08thus: tRP = [113(705) -10) ns= 225 nsRow Address Setup TimetASR = 1I2(tCLK) - tAD - tpLH(74LS373)- tPLH(74S157) + tRF- tPHL(74LS08)where: tCLK = 2 x WCLK cycle timetAD = Address/data delay from 2 x CCLK(MAX, 7220 Spec.)tRF = ALE delay from 2 x CCLK (MIN, 7220Spec.)thus: tASR = [1/2(705) - 130 - 18 - 7.5 + 20+ 4) ns= 221 nsRow Address Hold TimetRAH = 1I2(tCLK) - tPHL(74LS08)+ tPLH(74LS74) + tPHL(74S157)thus: tRAH = [1/2(705) - 20 + 6 + 6) ns= 344.5 nsCAS Access TimeA. DisplaytCAC = 7(tDCLK) - tPLH(74S163)- tPHL(74LS74) - tPHL(74LS139)- tsu(74S299)where: tDCLK = Dot clock cycle timethus: tCAC = [7(88) - 15 - 40 - 33 - 7) ns= 521 nsB. RMW cyclestCAC = 5.5(tCLKA) - tPHL(74S04)- tPHL(74LS74) - tPHL(74LS139)- tOIswhere: tCLKA = Clock A cycletOIs = Input data setup to 2 x CCLK (MIN,7220 Spec)thus: tCAC = [5.5(176) - 5 - 40 - 33 - 40) ns= 850 nsData Valid to Write EnabletDS = 112 (tcLK) - tAD - tPLH(74S04)+ tPLH(74LS74)thus: tDS = [112(705) - 5 - 130 + 6) ns= 223.5 nsRefresh IntervalFor this circuit the least significant address lines correspondto the DRAM row addresses which are incrementedevery display cycle. This provides a refresh rate given by:Refresh Interval = (256/number of display words)x line time= (256/32) x 63.5 p.s= .5 msTherefore the memory is refreshed by normal displayaccesses and the 7220 refresh feature is not needed for thisdesign.A comparison of the previous calculations to the DRAMspecification indicates there are no memory speed restrictionsfor the design. To attain the maximum speed of thisparticuI'ar design, Schottky components may be substitutedand the appropriate parameters placed into the above equationsto determine the maximum dot clock frequency. By usinghigh performance logic, a dot clock rate of approximately22 MHz can be used.co.~~...E..... o.5enco.~~.~Q.c.«9-33