1 - Al Kossow's Bitsavers

TMS4416/7220 GRAPIDCSAs the increased activity in computer graphics grows, theneed for dedicated graphics peripherals and video memorybecomes apparent. The NEC 7220 is currently a good answerfor a high resolution single chip graphics controller. The 7220provides all of the necessary graphics primatives for line,arc, and rectangle drawing, as well as area fill routines.Signal timings are easily adapted with extemallogic to providethe proper memory and video timings, with programmablefeatures allowing the user to do in software what hastypically been implemented in hardware. To take advantageof the 7220' s wide spectrum of operation requires a memorythat is also well adapted to graphics applications. TheTMS4416 16K x 4 dynamic RAM provides such a memory,with modularity and bandwidth advantages over 64K x 1memories. The architecture of the TMS4416 provides an outputenable function (relieving the need for databus buffers),faster access times and a 4X bandwidth improvement overXl devices of the same speed. Although 64K x 1 nibble modeparts out perform standard 64K x Is, they can not match thebandwidth of the TMS4416 and they require more memorycontrol circuitry to perform the same function. The modularityof the TMS4416 offers efficient memory usage in manyapplications and is well suited for both single and multi planememory systems.This application report describes a design coupling the7220 and the TMS4416 in a single plane, bit mapped graphicssystem. The main objective is to provide a detailed exampleof the necessary memory interface. While the design doesnot use all of the capabilities of the 7220 (DMA, Zoom, LightPen, etc.) .it does provide an easily adaptable example thatcan be tailored to many applications. This particular systemcan be switched between a 512 x 240 noninterlaced and512 x480 interlaced display by changing a single 7220parameter byte. To simplify the host interface an existingZ80A based computer was used to communicate to the 7220in a Multibus* system, with all the programming done inBASIC.To evaluate the design, calculations of the memory andvideo requirements will be given with a brief discussion ofkey points of interest. Measured drawing times for an arcand area fill are included to provide some feel for the drawingspeed of the 7220.Referring to the schematic (Figure 1), the graphics boardcan be divided into five functional blocks: Multibus* interface,7220, memory control, display memory, and video outputcircuitry. Four of the blocks will be discussed while adetailed understanding of the 7220 is left to the reader (NECprovides a 7220 Design Manual which is essential to understand7220 operation).A simple Multibus interface has been implemented forcontrol of the graphics system. The low order eight bits ofthe data bus are buffered with a 74LS640 transceiver. Thistransceiver is controlled by 10RC and output YO of the*Trademark of Intel Corporation.74LS138 (board select logic). The lU) and WR signals arederived from 10RC and rowc in conjunction with the boardselect. The XACK signal, required to terminate all liD operationsis generated by using the board select to enable a74LS241 whose input is tied to ground. The Multibus signaltimings were sufficient to meet the 7220 specificationswithout the use of complicated logic.The memory array is made up of four TMS4416s providing262,144 pixels. With the CAS circuitry shown, thememory space can be upgraded to sixteen TMS4416s for1,048,576 pixels which allows the maximum display resolution(1024 x 1024) of the 7220 to be implemented. TheTMS4416 offers improved modularity over the 64K xl(which relates to less wasted memory space) and is welladapted for multiplane memory systems. A four plane colorsystem of 512 x 512 display resolution requires sixteen 64KDRAMs. For the TMS4416 application, the memory breaksinto four physically separate planes which are simultaneouslyaccessed once per display cycle. With 64K x Is, the fourmemory planes reside in the same physical memory, and requirefour separate accesses to memory per display cycle.This significantly reduces the obtainable bandwidth and alsorequires the addition of complex control circuitry. The outputenable function and common liD of the TMS4416alleviate the need for databus buffering further reducing thecircuit component count.The memory control timing is generated by dividing thedot clock with a 74S163 and using the appropriate outputsto clock several 74LS74s for proper placement of the memorycontrol signals. This approach may seem complicated,however it allows maximum flexibility in generating the controlsignals by the choice of the clock connections. The fallingedge of ALE takes RAS low, latches the memory addressesand enables the 74LS74s in the memory control circuitry(see Figure 2). On the next rising edge of2 xWCLK(edge A), MUX goes low switching the memory addressesfrom row to column via two 74S157s. The row addressescorrespond to 7220 addresses AD-O through AD-7 and thecolumn addresses correspond to AD-8 through AD-13. Thenext rising edge of clock A (edge B) takes CASffi low.CASSTB is then used in conjunction with AD-14 and AD-15to derive four CAS signals through a 74LS139 for easymemory expansion. It is necessary to select the memory withCAS instead of RAS, because the 7220 does not provide astatus indicating the type of memory operation to be performed(display, refresh, or RMW). (Normally RAS is used formemory selection to reduce system power consumption andnoise induced by RAS switching currents.) The rising edgeof clock C (edge C) after CAS, takes the memory outputenable (G) signal low. The G signal is controlled such thatit is only active on display and RMW cycles; for refreshcycles, IT is held high by the 7220 DBIN and BLANKsignals. Generating four CAS signals and a single G signalt:o.~COE ...o-.5ent:o.~CO.~Q.c.«9-31