1 - Al Kossow's Bitsavers

Applications BriefTTL DRIVERS FOR THE TMS4416-15Some form of drive circuitry is needed when DRAMs are used with processors. such as the Z-80 or Z-8000. Onepossible solution involves the use of a precision delay line; however. a more cost-effective and efficient approachuses TTL devices as drivers. Two versions of TTL driver circuits are shown in Figures 1 and 2. The first figureshows the drive circuit for a memory array using TMS4416-1 5 DRAMs and the Z-80 processor; Figure 2 showsthe same array configured for use with the Z-8000 processor. Both circuits are designed to drive 256K bytes ofmemory arranged in either 8- or 1 6-bit words. They provide all DRAM control signals. address multiplexing. andrefresh address generation. The circuits shown for the Z-80 and the Z-8000 use the hidden refresh provided bythese devices so that refresh/access arbitration is not necessary. Time delays were selected to provide maximumperformance from the TMS4416-15 with off-the-shelf components. (Enhanced operation could be obtained byhand sel,ecting components for single applications.) A comparison of the two circuits will reve~1 the differencesbetween the two. The following description applies to both circuits.The memory array is arranged as 4 banks of 8 TMS4416s. Two TBP18S030 PROMs decode and generate thecontrol signals for the drive circuit. BAO and BA 1 are used to select which bank of memory will be accessed.MREQ and ACCESS are NORed and then delayed by 3 inverters to provide a CAS signal. The MUX Signal thatis used to switch the 74S153 multiplexers and propagate the column address to the memories is taken fromthe output of the first inverter in the CAS delay. CAS is connected to all the devices in the array. (Since RASacts as a chip enable. CAS will only activate the memories in the bank that has RAS active; this keeps the powerconsumption of the array lower than using CAS as select logic.) Two CAS drivers are used to reduce the effectsof the capacitive load of the DRAM CAS inputs. (This also improves drive characteristics and reduces noise.)Seri~s damping resistors have been added to reduce ringing on the address lines. These resistors should bebetween 15 and 68 ohms. depending on the circuit board layout. and can be determined by examining theaddress waveforms with an oscilloscope and selecting a value that produces the cleanest signal. The desired8- or 16-bit data word from the active bank is selected using RO. R 1. and the READ line. RO and Rl can beaddress lines from the Z-8001 or they can be generated from memory mapping logic. If the READ input is lowduring an access cycle. the output enable of the TMS4416 will be activated (RDA-RDD); a high input to READwill select a write output (WRA-WRD). Using this matrix. the memory can be divided into sixteen 16Kx8 oreight 16K x 16 blocks. The desired word width of the data output will be dependent on the microprocessorbeing used. For an 8-bit data bus the two data busses shown in the diagram would be connected in parallel.Since the Z-80 only directly accesses 64K of memory. bank select logic must be included in this memory systemto provide higher order address lines. The design of the bank select circuitry has been left up to the user. butmight include memory mapping or other logic.coo+:;COE ...o'+-.5encoo+:;COo~C.•Q.ct9-25