1 - Al Kossow's Bitsavers

PAD OPENINGIN OVERCOATPADMETALPADMET AL-TO-DIFFUSIONCONTACT OPENINGSP- p-VSS-METALP+FIGURE 2A -DIODE AND TRANSISTOR CLAMPING CIRCUITFIGURE 28 -CROSS SECTION OF CLAMPING CIRCUITThe essential element of the circuit is the input diode (A). which is surrounded by a diffused guard ring (B) connected to VSS.This circuit can be viewed as a combination of a lateral NPN transistor, a bipolar diode, and a thick field transistor - all occupyingthe same area and connected to the input pad. The P - /P + substrate is both the base of the transistor and the anodeof the diode. Both are connected to VSS through the resistance of the substrate from the surface of the chip to the backside.During an ESD with positive voltage, the input diffused area goes into reverse-bias breakdown, which turns on the bipolartransistor, thus clamping the input voltage. The action of the transistor is identical to second breakdown observed in conventionalbipolar transistors. Once the transistor turns on, it can sink a large amount of transient current which is evenlydistributed over the area of the input diffusion (collector of the lateral transistor). This avoids localized heating from theenergy in the ESD. Localized heating could destroy the integrity of the input diode. For ESD with negative voltage, the diodeand the transistor act to clamp the input voltage. When the input voltage drops below - 0.7 V, the input diffusion appears asa cathode for a diode tied through the substrate resistance to ground. It also acts as an emitter for the lateral NPN transistor.Both elements turn on and tend to uniformly source the current in the input diffusion. .The polysilicon resistor included in the input circuit serves to limit the amount of voltage that reaches the thin oxideassociated with the address buffers and clock inputs. The dynamic impedance of the input clamping circuit is considerablylower than the resistance of the polysilicon resistor.•The input circuit also offers the advantage of clamping negative undershoots on the inputs during normal operation. Whilethis provides advantage to the board and system designer, it can cause confusion for the test engineer unless he fullyunderstands the limits of his tester. DRAMs have historically been specified with negative dc input voltages of -1 V. In addition,they are often tested/characterized to - 3 V. This testing has been done to ensure that the devices will operate correctlywith a negative input undershoot, which is transient. Such testing was required due to the inability of a MOSFET ofreasonable size on the chip to clamp the negative-going input and due to the susceptibility of address input buffers on someMOS RAMs to negative input undershoots. The input clamping mechanism, provided on the TMS4164A and the TMS441 6,can supply sufficient current to clamp the input transient.Difficulty in testing the device with negative dc input voltages can occur due to the tester's output driver devices going intosaturation when forward biasing the input diode. Also, most testers are unable to supply the large transient current requirementduring reversal of bias on the input diode and transistor. Both effects will result in distortion of the tester's waveforms.What may appear to be poor setup and hold time margins of the device may actually be a tester's inability to supply the correctwaveforms to the device at the proper time.The improvement in both ESD protection and signal undershoot on system boards offered by the input circuit may beoverlooked if erroneous conclusions are drawn from incoming testing with negative dc input voltages below - O. 7 V.9-8