1 - Al Kossow's Bitsavers

Applications Brief64K DYNAMIC RAM REFRESH ANALYSISSYSTEM DESIGN CONSIDERATIONS64K SYSTEM HARDWARE64 KHZOSCILLATOR.REFRESHCONTROLLER64 KHzOSCILLATORREFRESHCONTROLL'ER128 CYCLE REFRES.H256 CYCLE REFRESH64K64K• 8 bit address mUltiplexing and8 bit address bus are needed foreither 256 or 128 cycle refreshon 64K.• 128 cycle 64K s require 1 lesscounter bit (7 vs. 8). This is, however,unlikely to be a practicalsaving since counters/multiplexerscome in 4 and 8 bit multiples.• 256 cycle/4 ms refresh approachaUows the same oscillator timing(64 kHz) to be used when upgradingfrom 16K s (128 cycle/2 ms period).• Systems designed for 256 cycle64K s can easily use 128 cycle64K s.Compatibility among all 64K Dynamic RAM vendors can be achieved by designing to TI's 416464K x 1 Dynamic RAM. The TMS 4164 requires all 256 rows to be refreshed within 4 ms. Competitive64K D RAMs which are not able to achieve the 256 cycle, 4 ms refresh rate require twicethe number of sense amplifiers as the TMS 4164 and half the number of refresh addresses. A 64KD RAM which requires the 128 cycle, 2 ms refresh treats the 256 cycle, 4 ms refresh as two refreshevents in 2 ms each.Simply:256 cycle in 4 ms = 2 (128 cycle in 2 ms)The extra address bit, A7, during refresh is treated by these vendors as a don't care situation.The TMS 4164 has the same refresh rate as the 4116, 16K x 1 Dynamic RAM, which requires128 rows to be refreshed in 2 ms. Most 4116 based systems already contain the extra refreshcounter bit required for upgrading to the 64K. Those implemented with the 74LS393; 8-bitcounter already do.co.~CO.. E....o.Eenco.~CO.5:aQ.c.