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TMS2150CACHE ADDRESS COMPARATORwrite cycle timing::~~~~~~~~~~~~~~~~~~~~~)~~~~~~~~~~~~~~~~~~~~::.l~.-- ADDRESS __ tc_(W __ VALID ~je----- th(A) ---t...... menc:r;lJl>s::m:::Ic..s::CD3o-
MOSLSITMS40162048·WORD BY 8·BIT STATIC RAMFEBRUARY 1981 - REVISED AUGUST 1983• 2K X a Organization. Common I/O• Single + 5-V Supply• Fully Static Operation (No Clocks. NoRefresh)• JEDEC Standard Pinout• 24-Pin 600 Mil (15.2 mm) PackageConfiguration• Plug-in Compatible with 16K 5 V EPROMs• a-Bit Output for Use in Microprocessor-Based Systems• 3-State Outputs with S for OR-ties• G Eliminates Need for External Bus Buffers• <strong>Al</strong>l Inputs and Outputs Fully TTL Compatible• Fanout to Series 74, Series 74S or Series74LS TTL Loads• N-Channel Silicon-Gate Technology• Power Dissipation Under 385 mW Max• Guaranteed dc Noise Immunity of 400 mVwith Standard TTL Loads• 4 Performance Ranges:TMS4016-12TMS4016-15TMS4016-20TMS4016-25ACCESS TIME (MAX)120 ns150 ns200 ns250 nsTMS40l6 ... NL PACKAGE(TOP VIEW)DalVeeASA9PIN NOMENCLATUREAO - A10AddressesDa1 - Das Data In/Data Out~Output EnableChip Select+5-V SupplyGroundWrite EnableSVeeVSSWenG)UoS;G)C1::o0.0.:::slen~oEG)~"0Cca~~descriptionThe TMS4016 static random-access memory is organized as 2048 words of 8 bits each. Fabricated using provenN-channel, silicon-gate MOS technology, the TMS4016 operates at high speeds and draws less power per bit than4K static RAMs. It is fully compatible with Series 74, 74S, or 74LS TTL. Its static design means that no refresh clockingcircuitry is needed and timing requirements are simplified. Access time is equal to cycle time. A chip select controlis provided for controlling the flow of data-in and data-out and an output enable function is included in order to eliminatethe need for external bus buffers.Of special importance is that the TMS4016 static RAM has the same standardized pinout as TI's compatible EPROMfamily. This, along with other compatible features, makes the TMS4016 plug-in compatible with the TMS2516 (orother 16K 5 V EPROMsl. Minimal, if any modifications are needed. This allows the microprocessor system designercomplete flexibility in partitioning his memory board between read/write and non-volatile storage.The TMS4016 is offered in the plastic (NL suffix) 24-pin dual-in-line package designed for insertion in mounting holerows on 600-mil (15.2 mm) centers. It is guaranteed for operation from ooe to 70°C.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated8-13
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SMYOOO2.,MOS MemoryData Book1984II
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ALPHANUMERIC INDEX TO DATA SHEETSSM
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TABLE OF CONTENTSALPHANUMERIC INDEX
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MOSLSIRAMs, ROMs, EPROMsSELECTION G
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If you want to give it a try for yo
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INTERCHANGEABILITY GUIDEPART 1 -ALT
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INTERCHANGEABILITY GUIDEFUJITSUMB 8
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INTERCHANGEABILITY GUIDEMOTOROLAMCM
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INTERCHANGEABILITY GUIDETOSHIBATMM
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INTERCHANGEABILITY GUIDESTATIC RAMS
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Alphanumeric Index, Table of Conten
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GLOSSARY fTIMING CONVENTIONS/DATA S
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GLOSSARY/TIMING CONVENTIONS/DATA SH
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GLOSSARY!TIMING CONVENTIONS/DATA SH
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MOSLSITMS411616,384-811 DYNAMIC RAN
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TMS411616,384·811 DYNAMIC RANDOM·
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1MS411616,384-811 DYNAMIC RANDOM-AC
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TMS411616.384·81T DYNAMIC RANDOM·
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zIiADDRESSES~!.....RASCASwDO"*. i,*
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TMS411616,384-81T DYNAMIC RANDOM-AC
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MOSLSITMS416165,536-81T MULTIPORT M
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TMS416165,536-811 MULTIPORT MEMORYf
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TMS416165,536-BIT MULTIPORT MEMORYs
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TMS416165,536-0IT MULTIPORT MEMORYc
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TMS416165,536·BIT MUL TIPORT MEMOR
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TMS416165,536 o BIT MUL TIPORT MEMO
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TMS416165,536·811 MULTIPORT MEMORY
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zI[~~~co,.. twiRL) _,RAS:::~ SI l L
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TMS416165,536·BIT MULTIPORT MEMORY
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~ ___TMS416165.536-BIT MUL TIPORT M
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0>~a~~i'i_';:;Z~~~d~c:::• s:~lTl~
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TMS416165,536-8IT MULTIPORT MEMORY1
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MOSLSITMS4164, SMJ416465,536-8IT DY
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TMS4164, SMJ416465,536-811. DYNAMIC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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SMJ416465,536-81T DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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TMS4164, SMJ416465,536·81T DYNAMIC
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TMS4164, SMJ416465,536·8IT DYNAMIC
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z~~gz~.J:>.c1J
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Z~d~~~~0,'...."CIIICCCD:3of. twIRL)
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MOSLSITMS4256. TMS4257262.144·8IT
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TMS4256, TMS4257262,144·8IT DYNAMI
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TMS4256, TMS4257262,144-8IT DYNAMIC
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TMS4257262.144·8IT DYNAMIC RANDOM
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TMS4256, TMS4257262,144·BIT DYNAMI
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TMS4257262,144·81T DYNAMIC RANDOM
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Z~d~~~~.!..JcoNOTE:'CIIICO(1),- twI
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i:Z~d~~z~+:>0Co ......"CCICCCD:3og.
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MOSLSITMS4416. SMJ441616.384·WORD
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TMS4416, SMJ441616,384·WORD BY 4·
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TMS441616,384-WORD BY 4-BI1 DYNAMIC
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TMS441616,384-WORD BY 4-BIT DYNAMIC
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SMJ441616,384·WORD BY 4·BIT DYNAM
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SMJ441616,384-WORD BY 4-B11 DYNAMIC
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1MS4416, SMJ441616,384·WORD BY 4·
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TMS4416, SMJ441616,384·WORD BY 4·
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z~~~z@towRAs-{rCASAO·A7wDQG:::'.!A
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1:'QltC(()3oc..(()C3~~n_:::Z~~~;;;
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MOSLSITMS446465,536-WORD BY 4-BIT D
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TMS446465,536-WORD 8Y 4-81T DYNAMIC
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TMS446465,536·WORD BY 4·BIT DYNAM
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1MS446465,536·WORD BY 4·B11 DYNAM
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TMS446465,536·WORD BY 4·BIT DYNAM
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RASCAS----{! '.,ReIVIH i~VIL I tRLC
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~~~n_;;;z~~. ~~tTlg ;O~d ;;;t::=z~@
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~Z~~iZ~tw '"[:;-~~~~~:TCDCO ".;:r0~
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MEMORY SUPPORTLSITMS4500ADYNAMIC RA
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TMS4500ADYNAMIC RAM CONTROLLERpin d
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TMS4500ADYNAMIC RAM CONTROLLERarbit
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TMS4500ADYNAMIC RAM CONTROLLERswitc
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TMS4500ADYNAMIC RAM CONTROLLERacces
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TMS4500ADYNAMIC RAM CONTROLLERoutpu
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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•••••MOSLSI65,536 X 4 Org
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TM4164EC465,536 BY 4·BIT DYNAMIC R
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MOSLSITM4164EL965,536 BY 9·BIT DYN
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TM4164EL965,536 BY 9-BIT DYNAMIC RA
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••••••••0MOSLSI65,5
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TM4164FL865,536 BY 8·BIT DYNAMIC R
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MOSLSITMS2516. SMJ251616.384-BIT ER
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TMS2516, SMJ251616,384-BIT ERASABLE
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TMS251616,384·BIT ERASABLE PROGRAM
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SMJ251616,384-BIT ERASABLE PROGRAMM
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o 441MS2516, SMJ251616,384·B11 ERA
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MOSLSITMS2532, SMJ253232,768·BIT E
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TMS253232,768-BI1 ERASABLE PROGRAMM
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MOSLSITMS2564, SMJ256465,536-BIT ER
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TMS256465,536-BIT ERASABLE PROGRAMM
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TMS2564 r SMJ256465 r536-BIT ERASAB
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MOSLSITMS2708, TMS27L08, SMJ2708, S
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TMS270B, TMS27LOBSMJ270B, SMJ27LOB1
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TMS2708. TMS27L081024·WORD BY 8·B
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SMJ2708, SMJ27L081024·WORD BY 8·B
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TMS2708, TMS27L08SMJ2708, SMJ27L081
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MOSLSITMS27162048·WORD BY 8·BIT E
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TMS27162048·WORD BY 8·BIT ERASABL
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TMS27162048-WORD BY 8-BIT ERASABLEP
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TMS2732A32,76B-BIT ERASABLE PROGRAM
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TMS2732A32,768-BIT ERASABLE PROGRAM
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TMS2732A32,768·BIT ERASABLE PROGRA
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MOSLSITMS276465,536-BI1 ERASABLE PR
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TMS276465,536·BIT ERASABLE PROGRAM
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MOSLSITMS27128131,072·BIT ERASABLE
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TMS27128131,072·BI1 ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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MOSLSITMS46648192·WORD BY 8·BIT R
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TMS46648192·WORD BY 8·BIT READ·O
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TMS46648192·WORD BY 8·BIT READ·O
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MOSLSITMS47324096~WORD BY B·BIT RE
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Page 285 and 286: MOSLSI, TMS49648192·WORD BY 8·BIT
Page 293 and 294: MOSLSITMS4712816,384·WORD BY 8·BI
Page 295 and 296: TMS4712816,384·WORD BY 8·BIT READ
Page 297 and 298: TMS4712816,384-WORD BY 8-BIT READ-O
Page 303 and 304: MOSLSITMS4725632.768·WORD BY 8·BI
Page 305 and 306: TMS4725632.768·WORD BY 8·BIT READ
Page 313 and 314: Alphanumeric Index, Table of Conten
Page 315 and 316: MOSLSITMS2114, TMS2114L1024·WORD B
Page 317 and 318: TMS2114, TMS2114L1024·WDRD BY 4·B
Page 319 and 320: TMS2114. TMS2114L1024·WORD BV 4·B
Page 321 and 322: ADVANCED MEMORYDEVELOPMENT•Fast A
Page 323 and 324: TMS2150CACHE ADDRESS COMPARATORabso
Page 325: TMS2150CACHE ADDRESS COMPARATORPARA
Page 329 and 330: TMS4016204H-WORD BY H-BIT STATIC RA
Page 331 and 332: TMS40162048-WDRD BY 8-BIT STATIC RA
Page 333 and 334: MOSLSITMS4044, TMS40L444096-WORD BY
Page 335 and 336: TMS4044, TMS40L444096·WORD BY 1·B
Page 337 and 338: TMS4044, TMS40L444096·WORD BY l·B
Page 339 and 340: MILITARYCMOSLSISMJ55172048-WORD BY
Page 341 and 342: SMJ5517204a·WORD BY a·BIT STATIC
Page 343 and 344: SMJ55172048·WORD BY 8·BIT STATIC
Page 345 and 346: SMJ55172048-WDRD BY 8-BIT STATIC RA
Page 347 and 348: SMJ5517204B·WORD BY B·BIT STATIC
Page 349: Alphanumeric Index, Table of Conten
Page 352 and 353: However, the TMS 4164 provides the
Page 354 and 355: EXPANSION OF 3242 FOR 256-CYCLE REF
Page 356 and 357: •9-6
Page 358 and 359: PAD OPENINGIN OVERCOATPADMETALPADME
Page 360 and 361: Figure 5 shows how the driver outpu
Page 362 and 363: cpI UO,leWJOJUI suo'le:>!ldd"f\)W(3
Page 364 and 365: The falling edge of RAS causes R 1
Page 366 and 367: ~--------::~~:~:~~~:--------~~7,34(
Page 368 and 369: J-Lead AdvantageTexas Instruments P
Page 370 and 371: Surface Mount Component Availabilit
Page 372 and 373: fiSECONDARYVAPOR(VAPOR BLANKET)..Fi
Page 374 and 375: l>'C'2.ri'Q),..o·:::Jen5'....... o
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l>"C'2..(i"Dl...0":=(I)5"....o...3D
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An external refresh counter has bee
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l>'C'CC:)"Q).-+o·::::sen:ro ... ""
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uo!~ew"oJul suo!~ea!ldd"CD .,.., w7
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DOTCLOCKCLOCK ACLOCK C2 xWCLKRAS (A
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B. If dynamic RAM refresh is enable
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•9-38
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The TMS4416/TMS4500A board is arran
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RAS ~CAS \ I2AI \ I '-2BI '-iiD1Ro2
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9-44
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ALEACXRASMAO-MA7CASFIGURE 1 -ALE LE
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The ALE high to ClK low time is giv
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ClKALEACXRASMAO-MA7CASREFREQROY•
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CDinN~1~12 MHzClKINClKOUTWE/iOclKRD
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UO!leWJOJUI SUOlle:ludd"com~'~,i'74
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coen(J)CLOCKWRITEREADROYALEA14-A5MS
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. Access Grant CyclesThe precharge
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whereta(C)tp(BFR)(-103 + tc2 - tp(B
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•9-62
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tt(REH)TCHLLtAEL-RELRAS rise time (
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. Refresh CyclesOn refresh cycles t
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wherethus,fCLKfCLKtCACfCLK[1/2 (tCA
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R/W approach does a normal read-mod
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II(0~""6 MHzI UO!leWJO,ulSUo!le:l!l
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ClKAlE.ACR\ ,----\,\ ,----R/W\ ,---
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4. Row address setup and hold timeT
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CLKrWRITE -------I.~ ..~---REFRESH-
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The read access time on access gran
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implementations in order to relieve
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"C'2..c:rm...o·j(I)....5'o3...mo·
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RELATIVE MEMORY SIZEARCHIVAL STORAG
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increments till satisfied. This pro
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In the example shown in Figure 5, t
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»'C"E..crQ)r+0':::Jtil:;-....o...3
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•9-94
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184LOGIC SYMBOLS1. INTRODUCTIONEXPl
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LOGIC SYMBOLS4.DIAGRAMATIC SUMMARYI
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lOGIC SYMBOLSWhen RAS goes low, it
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MECHANICAL DATAgeneralElectrical ch
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MECHANICAL DATAceramic packages -ce
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MECHANICAL DATAplastic packages (N
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MECHANICAL DATAceramic chip carrier
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Texas InstrumentsSemiconductor Tech
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TI Sales Offices TI DistributorsALA
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Printed in U.S.A.•TEXASINSTRUMENT
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