1 - Al Kossow's Bitsavers

ADVANCED MEMORYDEVELOPMENT•Fast Address to Match Valid Delay - TwoSpeed Ranges: 45 ns, 55 ns0 512 X 9 Internal RAMTMS2150CACHE ADDRESS COMPARATORMARCH 1982 - REVISED SEPTEMBER 1983TMS2150 ... JDL PACKAGE(TOP VIEW)0 300-Mil 24-Pin Ceramic Side BrazedPackage0 Max Power Dissipation: 660 mW•On-Chip Parity Generation and Checking0 Parity Error Output/Force Parity Error Input0 On-Chip Address/Data Comparator0 Asynchronous, Single-Cycle Reset0 Easily Expandable0 Fully Static, TTL Compatible0 Reliable SMOS (Scaled NMOS) TechnologydescriptionA5A3A2VSS-..... __VCCAlAOABA7A6D5D4D7D6MATCH..r- SThe S-bit-slice cache address comparator consists of a high-speed 51 2 X 9 static RAM array. parity generator. andparity checker. and 9-bit high-speed comparator. It is fabricated using N-channelsilicon gate technology for high speedand simple interface with MOS and bipolar TTL circuits. The cache address comparator is easily cascadable for widertag addresses or deeper tag memories. Significant reductions in cache memory component count. board area. andpower dissipation can be achieved with this device.When S is low and W is high. the cache address comparator compares the contents of the memory location addressedby AO-AS with the data on 00-07 plus generated parity. An equality is indicated by a high level on the MATCH output.A low-level output from PE signifies a parity error in the internal RAM data. PE is an N-channel open-drain output foreasy OR-tieing. During a write cycle (S and W lowl. data on 00-07 plus generated even parity are written in the 9-bitmemory location addressed by AO-AS. Also during write. a parity error may be forced by holding PE low.A RESET input is provided for initialization. When RESET goes low. all 51 2 X 9 RAM locations will be cleared and theMATCH output will be forced high.~...oc.C.::::Jen~oEQ)2"0Cm2«a:(,).~m~enThe cach~ address comparator operates from· a single + 5 V supply and is offered in a 24-pin 300-mil side brazedpackage. The device is fully TTL compatible and is guaranteed to operate from 0 DC to 70 DC.MATCH OUTPUT DESCRIPTIONFUNCTION TABLEMATCH = VOH if:or:or:or:MATCH = VOL if:[AO-AS) = 00-07 +parity.RESET = VIL.5 = VIH.IN = VIL[AO-AS) t 00-07 +parity.with RESET = VIH.5 = VIL. and VII = VIHOUTPUTFUNCTIONMATCH PE DESCRIPTIONL L Parity ErrorL H Not EqualH L Undefined ErrorH H Equal4TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated8-7