1 - Al Kossow's Bitsavers

TMS2114, TMS2114L1024-WORD BY 4-81T STATIC RAMSread-write cycle timingVIHADDRESS. AVIHWRITE ENABLE. WVILVIHCHIP SELECT. SVILVIHINPUT DATA. DVIL---xr----------...x"----VILf.- tsu(A) -toI th(A) j4 .. II \ Ije---i~tW(W)~""'S'-.,---~I---''t II IOUTPUT. aVOHVOLIIITYPICAL APPLICATION DATAEarly write cycle avoids DQ conflicts by controlling the write time with S. On the diagram above. the write operation willbe controlled by the leading edge of S. not W. Data can only be written when both Sand Ware low. Either S or W beinghigh inhibits the write operation. To prevent erroneous data being written into the array. the addresses must be stable duringthe write cycle as defined by tsu(A). tw(W). and th(A).Texas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.8-6TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 7526518·