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TMS2114, TMS2114L1024·WORD 8Y 4·81T STATIC RAMSoperationaddresses (AO - A9)The ten address inputs select one of the 1024 4-bit words in the RAM. The address inputs must be stable for theduration of a write cycle. The address inputs can be driven directly from standard Series 54/74 TTL with no externalpull-up resistors.chip select is)The chip-select terminal, which can be driven directly from standard TTL circuits, affects the data-in and data-outterminals. When chip select is at a logic low level, both terminals are enabled. When chip select is high, data-in isinhibited and data-out is in the floating or high-impedance state.write enable (W)The read or write mode is selected through the write enable terminal. A logic high selects the read mode; a logic lowselects the write mode. W or S must be high when changing addresses to prevent erroneously writing data into amemory location. The W input can be driven directly from standard TTL circuits.data-in/data-out (001 -OQ4)Data can be written into a selected device when the write enable input is low. The DO terminal can be driven directlyfrom standard TTL circuits. The three-state output buffer provides direct TTL compatibility with a fan-out of two Series74 TTL gates, one Series 74S TIL gate, or eight Series 74LS TTL gates. The DQ terminals are in the high-impedancestate when chip select (S) is high or whenever a write operation is being performed. Data-out is the same polarityas data-in.cCD
TMS2114, TMS2114L1024·WDRD BY 4·BIT STATIC RAMSlogic symboltRAM 1024x4(5)AO o ...(6)A1A2 (7)A3 (4)A4 (3)0A5 (2)>Ai023A6 (1)A7 (17)AS (16)A9 (15)9,S (S) -,....G1Vi (10) 1EN [READ)L:. 1C2 [WRITE)...., r001 (14) A,2DA,Z3k \73(13)002003 (12)004 (11)wLHXFUNCTION TABLES 001 - DQ4 MODEL VALID DATA WRITEL DATA OUTPUT READH HI-Z DEVICE DISABLEDtThis symbol is in accordance with IEEE Std 91/ANSI Y32.14 andrecent decisions by IEEE and lEe. See explanation on page 10-1.absolute maximum ratings over operating free·air temperature (unless otherwise noted) tSupply voltage, VCC (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 VInput voltage (any input) (see Note 1) ............................................. - 1 V to 7 VContinuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 WOperating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70°CStorage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 150°CU)(1)(,)'S(1)c~oc.C.::l(/)~oE(1)~"'CCm~cd:a:(,)'';:;m...(/)t Stresses beyond those listed under" Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specificationis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTE 1: Voltage values are with respect to the ground material.recommended operating conditionsTMS2114PARAMETER TMS2114L UNITMIN NOM MAXSupply voltage, VCC 4.5 5 5.5 VSupply voltage, VSS 0 VHigh-level input voltage, VIH 2 5.5 VLow-level input voltage, VIL (see Note 2) -1 O.B VOperating free-air temperature, T A 0 70 °cNOTE 2:The algebraic convention, where the more negative (less positive) limit is designated as minium, is used in this data sheet for logic voltage levels only.84TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752658-3
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SMYOOO2.,MOS MemoryData Book1984II
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ALPHANUMERIC INDEX TO DATA SHEETSSM
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TABLE OF CONTENTSALPHANUMERIC INDEX
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MOSLSIRAMs, ROMs, EPROMsSELECTION G
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If you want to give it a try for yo
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INTERCHANGEABILITY GUIDEPART 1 -ALT
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INTERCHANGEABILITY GUIDEFUJITSUMB 8
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INTERCHANGEABILITY GUIDEMOTOROLAMCM
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INTERCHANGEABILITY GUIDETOSHIBATMM
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INTERCHANGEABILITY GUIDESTATIC RAMS
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Alphanumeric Index, Table of Conten
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GLOSSARY fTIMING CONVENTIONS/DATA S
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GLOSSARY/TIMING CONVENTIONS/DATA SH
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GLOSSARY!TIMING CONVENTIONS/DATA SH
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MOSLSITMS411616,384-811 DYNAMIC RAN
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TMS411616,384·811 DYNAMIC RANDOM·
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1MS411616,384-811 DYNAMIC RANDOM-AC
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TMS411616.384·81T DYNAMIC RANDOM·
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zIiADDRESSES~!.....RASCASwDO"*. i,*
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TMS411616,384-81T DYNAMIC RANDOM-AC
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MOSLSITMS416165,536-81T MULTIPORT M
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TMS416165,536-811 MULTIPORT MEMORYf
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TMS416165,536-BIT MULTIPORT MEMORYs
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TMS416165,536-0IT MULTIPORT MEMORYc
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TMS416165,536·BIT MUL TIPORT MEMOR
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TMS416165,536 o BIT MUL TIPORT MEMO
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TMS416165,536·811 MULTIPORT MEMORY
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zI[~~~co,.. twiRL) _,RAS:::~ SI l L
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TMS416165,536·BIT MULTIPORT MEMORY
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~ ___TMS416165.536-BIT MUL TIPORT M
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0>~a~~i'i_';:;Z~~~d~c:::• s:~lTl~
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TMS416165,536-8IT MULTIPORT MEMORY1
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MOSLSITMS4164, SMJ416465,536-8IT DY
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TMS4164, SMJ416465,536-811. DYNAMIC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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SMJ416465,536-81T DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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TMS4164, SMJ416465,536·81T DYNAMIC
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TMS4164, SMJ416465,536·8IT DYNAMIC
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z~~gz~.J:>.c1J
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Z~d~~~~0,'...."CIIICCCD:3of. twIRL)
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MOSLSITMS4256. TMS4257262.144·8IT
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TMS4256, TMS4257262,144·8IT DYNAMI
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TMS4256, TMS4257262,144-8IT DYNAMIC
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TMS4257262.144·8IT DYNAMIC RANDOM
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TMS4256, TMS4257262,144·BIT DYNAMI
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TMS4257262,144·81T DYNAMIC RANDOM
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Z~d~~~~.!..JcoNOTE:'CIIICO(1),- twI
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i:Z~d~~z~+:>0Co ......"CCICCCD:3og.
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MOSLSITMS4416. SMJ441616.384·WORD
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TMS4416, SMJ441616,384·WORD BY 4·
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TMS441616,384-WORD BY 4-BI1 DYNAMIC
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TMS441616,384-WORD BY 4-BIT DYNAMIC
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SMJ441616,384·WORD BY 4·BIT DYNAM
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SMJ441616,384-WORD BY 4-B11 DYNAMIC
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1MS4416, SMJ441616,384·WORD BY 4·
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TMS4416, SMJ441616,384·WORD BY 4·
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z~~~z@towRAs-{rCASAO·A7wDQG:::'.!A
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1:'QltC(()3oc..(()C3~~n_:::Z~~~;;;
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MOSLSITMS446465,536-WORD BY 4-BIT D
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TMS446465,536-WORD 8Y 4-81T DYNAMIC
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TMS446465,536·WORD BY 4·BIT DYNAM
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1MS446465,536·WORD BY 4·B11 DYNAM
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TMS446465,536·WORD BY 4·BIT DYNAM
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RASCAS----{! '.,ReIVIH i~VIL I tRLC
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~~~n_;;;z~~. ~~tTlg ;O~d ;;;t::=z~@
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~Z~~iZ~tw '"[:;-~~~~~:TCDCO ".;:r0~
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MEMORY SUPPORTLSITMS4500ADYNAMIC RA
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TMS4500ADYNAMIC RAM CONTROLLERpin d
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TMS4500ADYNAMIC RAM CONTROLLERarbit
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TMS4500ADYNAMIC RAM CONTROLLERswitc
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TMS4500ADYNAMIC RAM CONTROLLERacces
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TMS4500ADYNAMIC RAM CONTROLLERoutpu
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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•••••MOSLSI65,536 X 4 Org
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TM4164EC465,536 BY 4·BIT DYNAMIC R
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MOSLSITM4164EL965,536 BY 9·BIT DYN
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TM4164EL965,536 BY 9-BIT DYNAMIC RA
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••••••••0MOSLSI65,5
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TM4164FL865,536 BY 8·BIT DYNAMIC R
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MOSLSITMS2516. SMJ251616.384-BIT ER
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TMS2516, SMJ251616,384-BIT ERASABLE
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TMS251616,384·BIT ERASABLE PROGRAM
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SMJ251616,384-BIT ERASABLE PROGRAMM
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o 441MS2516, SMJ251616,384·B11 ERA
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MOSLSITMS2532, SMJ253232,768·BIT E
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TMS253232,768-BI1 ERASABLE PROGRAMM
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MOSLSITMS2564, SMJ256465,536-BIT ER
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TMS256465,536-BIT ERASABLE PROGRAMM
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TMS2564 r SMJ256465 r536-BIT ERASAB
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MOSLSITMS2708, TMS27L08, SMJ2708, S
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TMS270B, TMS27LOBSMJ270B, SMJ27LOB1
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TMS2708. TMS27L081024·WORD BY 8·B
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SMJ2708, SMJ27L081024·WORD BY 8·B
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TMS2708, TMS27L08SMJ2708, SMJ27L081
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MOSLSITMS27162048·WORD BY 8·BIT E
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TMS27162048·WORD BY 8·BIT ERASABL
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TMS27162048-WORD BY 8-BIT ERASABLEP
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TMS2732A32,76B-BIT ERASABLE PROGRAM
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TMS2732A32,768-BIT ERASABLE PROGRAM
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TMS2732A32,768·BIT ERASABLE PROGRA
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MOSLSITMS276465,536-BI1 ERASABLE PR
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TMS276465,536·BIT ERASABLE PROGRAM
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MOSLSITMS27128131,072·BIT ERASABLE
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TMS27128131,072·BI1 ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
Page 265 and 266: Alphanumeric Index, Table of Conten
Page 267 and 268: MOSLSITMS46648192·WORD BY 8·BIT R
Page 269 and 270: TMS46648192·WORD BY 8·BIT READ·O
Page 273 and 274: MOSLSITMS47324096~WORD BY B·BIT RE
Page 279 and 280: MOSLSITMS47648192·WORD BY 8·BIT R
Page 285 and 286: MOSLSI, TMS49648192·WORD BY 8·BIT
Page 293 and 294: MOSLSITMS4712816,384·WORD BY 8·BI
Page 295 and 296: TMS4712816,384·WORD BY 8·BIT READ
Page 297 and 298: TMS4712816,384-WORD BY 8-BIT READ-O
Page 303 and 304: MOSLSITMS4725632.768·WORD BY 8·BI
Page 305 and 306: TMS4725632.768·WORD BY 8·BIT READ
Page 313 and 314: Alphanumeric Index, Table of Conten
Page 315: MOSLSITMS2114, TMS2114L1024·WORD B
Page 319 and 320: TMS2114. TMS2114L1024·WORD BV 4·B
Page 321 and 322: ADVANCED MEMORYDEVELOPMENT•Fast A
Page 323 and 324: TMS2150CACHE ADDRESS COMPARATORabso
Page 325 and 326: TMS2150CACHE ADDRESS COMPARATORPARA
Page 327 and 328: MOSLSITMS40162048·WORD BY 8·BIT S
Page 329 and 330: TMS4016204H-WORD BY H-BIT STATIC RA
Page 331 and 332: TMS40162048-WDRD BY 8-BIT STATIC RA
Page 333 and 334: MOSLSITMS4044, TMS40L444096-WORD BY
Page 335 and 336: TMS4044, TMS40L444096·WORD BY 1·B
Page 337 and 338: TMS4044, TMS40L444096·WORD BY l·B
Page 339 and 340: MILITARYCMOSLSISMJ55172048-WORD BY
Page 341 and 342: SMJ5517204a·WORD BY a·BIT STATIC
Page 343 and 344: SMJ55172048·WORD BY 8·BIT STATIC
Page 345 and 346: SMJ55172048-WDRD BY 8-BIT STATIC RA
Page 347 and 348: SMJ5517204B·WORD BY B·BIT STATIC
Page 349: Alphanumeric Index, Table of Conten
Page 352 and 353: However, the TMS 4164 provides the
Page 354 and 355: EXPANSION OF 3242 FOR 256-CYCLE REF
Page 356 and 357: •9-6
Page 358 and 359: PAD OPENINGIN OVERCOATPADMETALPADME
Page 360 and 361: Figure 5 shows how the driver outpu
Page 362 and 363: cpI UO,leWJOJUI suo'le:>!ldd"f\)W(3
Page 364 and 365: The falling edge of RAS causes R 1
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~--------::~~:~:~~~:--------~~7,34(
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J-Lead AdvantageTexas Instruments P
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Surface Mount Component Availabilit
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fiSECONDARYVAPOR(VAPOR BLANKET)..Fi
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l>'C'2.ri'Q),..o·:::Jen5'....... o
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l>"C'2..(i"Dl...0":=(I)5"....o...3D
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An external refresh counter has bee
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l>'C'CC:)"Q).-+o·::::sen:ro ... ""
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uo!~ew"oJul suo!~ea!ldd"CD .,.., w7
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DOTCLOCKCLOCK ACLOCK C2 xWCLKRAS (A
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B. If dynamic RAM refresh is enable
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•9-38
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The TMS4416/TMS4500A board is arran
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RAS ~CAS \ I2AI \ I '-2BI '-iiD1Ro2
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9-44
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ALEACXRASMAO-MA7CASFIGURE 1 -ALE LE
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The ALE high to ClK low time is giv
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ClKALEACXRASMAO-MA7CASREFREQROY•
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CDinN~1~12 MHzClKINClKOUTWE/iOclKRD
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UO!leWJOJUI SUOlle:ludd"com~'~,i'74
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coen(J)CLOCKWRITEREADROYALEA14-A5MS
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. Access Grant CyclesThe precharge
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whereta(C)tp(BFR)(-103 + tc2 - tp(B
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•9-62
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tt(REH)TCHLLtAEL-RELRAS rise time (
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. Refresh CyclesOn refresh cycles t
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wherethus,fCLKfCLKtCACfCLK[1/2 (tCA
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R/W approach does a normal read-mod
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II(0~""6 MHzI UO!leWJO,ulSUo!le:l!l
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ClKAlE.ACR\ ,----\,\ ,----R/W\ ,---
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4. Row address setup and hold timeT
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CLKrWRITE -------I.~ ..~---REFRESH-
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The read access time on access gran
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implementations in order to relieve
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"C'2..c:rm...o·j(I)....5'o3...mo·
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RELATIVE MEMORY SIZEARCHIVAL STORAG
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increments till satisfied. This pro
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In the example shown in Figure 5, t
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»'C"E..crQ)r+0':::Jtil:;-....o...3
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•9-94
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184LOGIC SYMBOLS1. INTRODUCTIONEXPl
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LOGIC SYMBOLS4.DIAGRAMATIC SUMMARYI
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lOGIC SYMBOLSWhen RAS goes low, it
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MECHANICAL DATAgeneralElectrical ch
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MECHANICAL DATAceramic packages -ce
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MECHANICAL DATAplastic packages (N
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MECHANICAL DATAceramic chip carrier
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Texas InstrumentsSemiconductor Tech
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TI Sales Offices TI DistributorsALA
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Printed in U.S.A.•TEXASINSTRUMENT
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