1 - Al Kossow's Bitsavers

MOSLSITMS4725632.768·WORD BY 8·BIT READ·ONLY MEMORYJUNE 1983• 32,768 X 8 Organization• Fully Static (No clocks, No Refresh)• All Inputs and Outputs TTL Compatible• Single 5·V Power Supply• Optional Power Down or Chip Select• 64K Bank Select Option• Maximum Access Time from Address orPower Down:TMS47256-25TMS47256-35TMS47256-45250 ns350 ns450 ns• Worst Case Active PowerDissipation .•. 330 mW• Worst Case Standby PowerDissipation ... 66 mWdescriptionThe TMS47256 is a 262, 144-bit read-only memoryorganized as 32,768 words of 8-bit length. This makesthe TMS47256 ideal for microprocessor basedsystems. The device is fabricated using N-channelsilicon-gate technology for high speed and simple interfacewith bipolar circuits.There are two versions of the TMS47256: the standardROM with options on chip selects and powerdown, and the bank select ROM with similar options.The operation section of this data sheet describes bothversions.TMS47256 ••• JL OR NL PACKAGE tSTANDARD ROM(TOP VIEWINC 1 U28 VCCA12A7232726A14A13A6 r4 25 A8A5A4562423A9AllA3 ~7 22 Sl/SlA2 8 21 Al0Al ;;;920t:: E/E/S2/S2AOQl10111918Q8Q7Q2 =1217~ Q6Q3 13 16 Q5VSS [14 15J Q4t The package for the bank select ROM is shown on page 2.PIN NOMENCLATURESTANDARD ROMAO-A14 AddressesE/E/52/S2 Chip Enable/Power Down or Chip SelectNCNo Connection0l-Q8 Data Out51/51 Chip SelectVCC+5-V SupplyVSSGroundenQ)CJ'S;Q)C~0a:The TMS47256 is fully compatible with Series 74, 74S, or 74LS TTL. The data outputs are three-state for OR-tieingmultiple devices on a common bus. Pins 20 and 22 are mask-programmable, providing additional system flexibility.The data is always available, it is not dependent on external clocking of pins 20 and 22.The TMS47256 is designed for high-density fixed-memory applications such as logic function generation andmicroprogramming. It is pin compatible with TI's full line of ROMs and EPROMs.This ROM is supplied in 28-pin dual-in-line plastic (NL suffix) or ceramic. (JL suffix) packages designed for insertionin mounting-hole rows on 600 mil centers. The device is designed for operation from O°C to 70 0 C.operation, standard ROMaddress (AO-A 14)The address-valid interval determines the device cycle time. The 15-bit positive-logic address is decoded on-chip toselect one of 32,768 words of 8-bit length in the memory array. AO is the least-significant bit and A 14 the mostsignificantbit of the word address.chip select (S1 or 51)Pin 22 can be programmed during mask fabrication to be active with either a high- or low-level input. When the signal14PRODUCT PREVIEWThis document contains information on 8 product underdevelopment. Texas Instruments reserves the right tochange or discontinue this product without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated7-37