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GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTUREMask-Programmed Read-Only Memory - A read-only memory in which the data content of each cell is determined duringmanufacture by the use of a mask. the data content thereafter being unalterable.Memory - A medium capable of storage of information from which the information can be retrieved.Memory Cell - The smallest subdivision of a memory into which a unit of data has been or can be entered. in which it is orcan be stored. and from which it can be retrieved.Metal-Oxide Semiconductor (MOS) -semiconductor device.The technology involving photolithographic layering of metal and oxide to produce aNMOS - A type of MOS technology in which the basic conduction mechanism is governed by electrons. (Short forN-channel MOS)G)5"enenQ)-
GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTUREVery-Large-Scale Integration (VLS!) - The description of any IC technology that is much more complex than large-scale integration(LSI), and involves a much higher equivalent gate count. At this time an exact definition including a minimumgate count has not been standardized by JEDEC or the IEEE.Volatile Memory -A memory in which the data content is lost when power supplied is disconnected.Word -Write -A series of one or more bits that occupy a given address location and that can be stored and retrieved in parallel.A memory operation whereby data is written into a desired address location.Write Enable - A control signal that when true causes the memory to assume the write mode, and when false causes it toassume the read mode.PART 11- OPERATING CONDITIONS AND CHARACTERISTICS (INCLUDING LETTER SYMBOLS)CapacitanceCurrentThe inherent capacitance on every pin, which can vary with various inputs and outputs.Example symbology:Ci Input capacitanceCo Output capacitanceCi(D) Input capacitance, data inputHigh-level input current, IIHThe current into an input when a high-level voltage is applied-to that input.High-level output current, 10HThe current into * an output with input conditions applied that according to the product specification will establish a·hig!;l level at the output.Low-level input current, IlLThe current into an input when a low-level voltage is applied to that input.Low-level output current, 10LThe current into * an output with input conditions applied that according to the product specification will establish alow level at the output.Off-state Ihigh-impedance-state) output current lof a three-state output), 10ZThe current into * an output having three-state capability with input conditions applied that according to the productspecification will establish the high-impedance state at the output.Short-circuit output current, lOSThe current into * an output when the output is short-circuited to ground lor other specified potential) with input conditionsapplied to establish the output logic level farthest from ground potential (or other specified potential).Supply current IBB' ICC, 100, IppThe current into, respectively, the VBB, VCC, VDD, Vpp supply terminals.Operating Free-Air TemperatureQ).....::s(.).. ::s...CJ)...Q)Q)..c:CJ)...COCOQ-enco"+:cQ)>Co(.)C)C"si=-~COeneno(5The temperature (T A) range over which the device will operate and meet the specified electrical characteristics.Operating Case TemperatureThe case temperature IT C) range over which the device will operate and meet the specified electrical characteristics." Current out of a terminal is given as a negative value.TEXAS INSTRUMENTSINCORPORATEDPOST OFFICE BOX 225012 • DALLAS, TEXAS 752653-3
Page 1: SMYOOO2.,MOS MemoryData Book1984II
Page 9 and 10: ALPHANUMERIC INDEX TO DATA SHEETSSM
Page 11 and 12: TABLE OF CONTENTSALPHANUMERIC INDEX
Page 13 and 14: MOSLSIRAMs, ROMs, EPROMsSELECTION G
Page 15 and 16: If you want to give it a try for yo
Page 17 and 18: INTERCHANGEABILITY GUIDEPART 1 -ALT
Page 19 and 20: INTERCHANGEABILITY GUIDEFUJITSUMB 8
Page 21 and 22: INTERCHANGEABILITY GUIDEMOTOROLAMCM
Page 23 and 24: INTERCHANGEABILITY GUIDETOSHIBATMM
Page 25 and 26: INTERCHANGEABILITY GUIDESTATIC RAMS
Page 27 and 28: Alphanumeric Index, Table of Conten
Page 29: GLOSSARY fTIMING CONVENTIONS/DATA S
Page 33 and 34: GLOSSARY!TIMING CONVENTIONS/DATA SH
Page 35 and 36: GLOSSARY/TIMING CONVENTIONS/DATA SH
Page 37 and 38: GLOSSARY/TIMING CONVENTIONS/DATA SH
Page 39 and 40: Alphanumeric Index, Table of Conten
Page 41 and 42: MOSLSITMS411616,384-811 DYNAMIC RAN
Page 43 and 44: TMS411616,384·811 DYNAMIC RANDOM·
Page 45 and 46: 1MS411616,384-811 DYNAMIC RANDOM-AC
Page 47 and 48: TMS411616.384·81T DYNAMIC RANDOM·
Page 49 and 50: TMS411616,384·811 DYNAMIC RANDOM·
Page 51 and 52: zIiADDRESSES~!.....RASCASwDO"*. i,*
Page 53 and 54: TMS411616,384-81T DYNAMIC RANDOM-AC
Page 55 and 56: MOSLSITMS416165,536-81T MULTIPORT M
Page 57 and 58: TMS416165,536-811 MULTIPORT MEMORYf
Page 59 and 60: TMS416165,536-BIT MULTIPORT MEMORYs
Page 61 and 62: TMS416165,536-0IT MULTIPORT MEMORYc
Page 63 and 64: TMS416165,536·BIT MUL TIPORT MEMOR
Page 65 and 66: TMS416165,536 o BIT MUL TIPORT MEMO
Page 67 and 68: TMS416165,536·811 MULTIPORT MEMORY
Page 69 and 70: zI[~~~co,.. twiRL) _,RAS:::~ SI l L
Page 71 and 72: TMS416165,536·BIT MULTIPORT MEMORY
Page 73 and 74: ~ ___TMS416165.536-BIT MUL TIPORT M
Page 75 and 76: 0>~a~~i'i_';:;Z~~~d~c:::• s:~lTl~
Page 77 and 78: TMS416165,536-8IT MULTIPORT MEMORY1
Page 79 and 80: MOSLSITMS4164, SMJ416465,536-8IT DY
Page 81 and 82:
TMS4164, SMJ416465,536-811. DYNAMIC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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TMS416465,536·811 DYNAMIC RANDOM·
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TMS416465,536-811 DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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SMJ416465,536-81T DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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TMS4164, SMJ416465,536·81T DYNAMIC
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TMS4164, SMJ416465,536·8IT DYNAMIC
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z~~gz~.J:>.c1J
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Z~d~~~~0,'...."CIIICCCD:3of. twIRL)
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MOSLSITMS4256. TMS4257262.144·8IT
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TMS4256, TMS4257262,144·8IT DYNAMI
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TMS4256, TMS4257262,144-8IT DYNAMIC
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TMS4257262.144·8IT DYNAMIC RANDOM
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TMS4256, TMS4257262,144·BIT DYNAMI
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TMS4257262,144·81T DYNAMIC RANDOM
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Z~d~~~~.!..JcoNOTE:'CIIICO(1),- twI
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i:Z~d~~z~+:>0Co ......"CCICCCD:3og.
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MOSLSITMS4416. SMJ441616.384·WORD
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TMS4416, SMJ441616,384·WORD BY 4·
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TMS441616,384-WORD BY 4-BI1 DYNAMIC
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TMS441616,384-WORD BY 4-BIT DYNAMIC
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SMJ441616,384·WORD BY 4·BIT DYNAM
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SMJ441616,384-WORD BY 4-B11 DYNAMIC
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1MS4416, SMJ441616,384·WORD BY 4·
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TMS4416, SMJ441616,384·WORD BY 4·
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z~~~z@towRAs-{rCASAO·A7wDQG:::'.!A
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1:'QltC(()3oc..(()C3~~n_:::Z~~~;;;
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MOSLSITMS446465,536-WORD BY 4-BIT D
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TMS446465,536-WORD 8Y 4-81T DYNAMIC
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TMS446465,536·WORD BY 4·BIT DYNAM
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1MS446465,536·WORD BY 4·B11 DYNAM
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TMS446465,536·WORD BY 4·BIT DYNAM
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RASCAS----{! '.,ReIVIH i~VIL I tRLC
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~~~n_;;;z~~. ~~tTlg ;O~d ;;;t::=z~@
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~Z~~iZ~tw '"[:;-~~~~~:TCDCO ".;:r0~
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MEMORY SUPPORTLSITMS4500ADYNAMIC RA
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TMS4500ADYNAMIC RAM CONTROLLERpin d
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TMS4500ADYNAMIC RAM CONTROLLERarbit
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TMS4500ADYNAMIC RAM CONTROLLERswitc
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TMS4500ADYNAMIC RAM CONTROLLERacces
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TMS4500ADYNAMIC RAM CONTROLLERoutpu
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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Alphanumeric Index, Table of Conten
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•••••MOSLSI65,536 X 4 Org
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TM4164EC465,536 BY 4·BIT DYNAMIC R
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MOSLSITM4164EL965,536 BY 9·BIT DYN
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TM4164EL965,536 BY 9-BIT DYNAMIC RA
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••••••••0MOSLSI65,5
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TM4164FL865,536 BY 8·BIT DYNAMIC R
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MOSLSITMS2516. SMJ251616.384-BIT ER
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TMS2516, SMJ251616,384-BIT ERASABLE
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TMS251616,384·BIT ERASABLE PROGRAM
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SMJ251616,384-BIT ERASABLE PROGRAMM
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o 441MS2516, SMJ251616,384·B11 ERA
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MOSLSITMS2532, SMJ253232,768·BIT E
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TMS253232,768-BI1 ERASABLE PROGRAMM
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MOSLSITMS2564, SMJ256465,536-BIT ER
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TMS256465,536-BIT ERASABLE PROGRAMM
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TMS2564 r SMJ256465 r536-BIT ERASAB
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MOSLSITMS2708, TMS27L08, SMJ2708, S
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TMS270B, TMS27LOBSMJ270B, SMJ27LOB1
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TMS2708. TMS27L081024·WORD BY 8·B
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SMJ2708, SMJ27L081024·WORD BY 8·B
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TMS2708, TMS27L08SMJ2708, SMJ27L081
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MOSLSITMS27162048·WORD BY 8·BIT E
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TMS27162048·WORD BY 8·BIT ERASABL
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TMS27162048-WORD BY 8-BIT ERASABLEP
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TMS2732A32,76B-BIT ERASABLE PROGRAM
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TMS2732A32,768-BIT ERASABLE PROGRAM
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TMS2732A32,768·BIT ERASABLE PROGRA
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MOSLSITMS276465,536-BI1 ERASABLE PR
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TMS276465,536·BIT ERASABLE PROGRAM
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MOSLSITMS27128131,072·BIT ERASABLE
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TMS27128131,072·BI1 ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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MOSLSITMS46648192·WORD BY 8·BIT R
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TMS46648192·WORD BY 8·BIT READ·O
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MOSLSITMS47324096~WORD BY B·BIT RE
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MOSLSITMS47648192·WORD BY 8·BIT R
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MOSLSI, TMS49648192·WORD BY 8·BIT
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MOSLSITMS4712816,384·WORD BY 8·BI
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TMS4712816,384·WORD BY 8·BIT READ
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TMS4712816,384-WORD BY 8-BIT READ-O
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Page 301 and 302:
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MOSLSITMS4725632.768·WORD BY 8·BI
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TMS4725632.768·WORD BY 8·BIT READ
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Page 313 and 314:
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MOSLSITMS2114, TMS2114L1024·WORD B
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TMS2114, TMS2114L1024·WDRD BY 4·B
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TMS2114. TMS2114L1024·WORD BV 4·B
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ADVANCED MEMORYDEVELOPMENT•Fast A
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TMS2150CACHE ADDRESS COMPARATORabso
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TMS2150CACHE ADDRESS COMPARATORPARA
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MOSLSITMS40162048·WORD BY 8·BIT S
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TMS4016204H-WORD BY H-BIT STATIC RA
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TMS40162048-WDRD BY 8-BIT STATIC RA
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MOSLSITMS4044, TMS40L444096-WORD BY
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TMS4044, TMS40L444096·WORD BY 1·B
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TMS4044, TMS40L444096·WORD BY l·B
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MILITARYCMOSLSISMJ55172048-WORD BY
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SMJ5517204a·WORD BY a·BIT STATIC
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SMJ55172048·WORD BY 8·BIT STATIC
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SMJ55172048-WDRD BY 8-BIT STATIC RA
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SMJ5517204B·WORD BY B·BIT STATIC
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However, the TMS 4164 provides the
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EXPANSION OF 3242 FOR 256-CYCLE REF
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•9-6
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PAD OPENINGIN OVERCOATPADMETALPADME
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Figure 5 shows how the driver outpu
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cpI UO,leWJOJUI suo'le:>!ldd"f\)W(3
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The falling edge of RAS causes R 1
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~--------::~~:~:~~~:--------~~7,34(
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J-Lead AdvantageTexas Instruments P
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Surface Mount Component Availabilit
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fiSECONDARYVAPOR(VAPOR BLANKET)..Fi
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l>'C'2.ri'Q),..o·:::Jen5'....... o
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l>"C'2..(i"Dl...0":=(I)5"....o...3D
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An external refresh counter has bee
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l>'C'CC:)"Q).-+o·::::sen:ro ... ""
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uo!~ew"oJul suo!~ea!ldd"CD .,.., w7
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DOTCLOCKCLOCK ACLOCK C2 xWCLKRAS (A
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B. If dynamic RAM refresh is enable
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•9-38
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The TMS4416/TMS4500A board is arran
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RAS ~CAS \ I2AI \ I '-2BI '-iiD1Ro2
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9-44
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ALEACXRASMAO-MA7CASFIGURE 1 -ALE LE
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The ALE high to ClK low time is giv
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ClKALEACXRASMAO-MA7CASREFREQROY•
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CDinN~1~12 MHzClKINClKOUTWE/iOclKRD
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UO!leWJOJUI SUOlle:ludd"com~'~,i'74
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coen(J)CLOCKWRITEREADROYALEA14-A5MS
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. Access Grant CyclesThe precharge
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whereta(C)tp(BFR)(-103 + tc2 - tp(B
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•9-62
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tt(REH)TCHLLtAEL-RELRAS rise time (
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. Refresh CyclesOn refresh cycles t
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wherethus,fCLKfCLKtCACfCLK[1/2 (tCA
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R/W approach does a normal read-mod
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II(0~""6 MHzI UO!leWJO,ulSUo!le:l!l
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ClKAlE.ACR\ ,----\,\ ,----R/W\ ,---
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4. Row address setup and hold timeT
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CLKrWRITE -------I.~ ..~---REFRESH-
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The read access time on access gran
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implementations in order to relieve
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"C'2..c:rm...o·j(I)....5'o3...mo·
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RELATIVE MEMORY SIZEARCHIVAL STORAG
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increments till satisfied. This pro
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In the example shown in Figure 5, t
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»'C"E..crQ)r+0':::Jtil:;-....o...3
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•9-94
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184LOGIC SYMBOLS1. INTRODUCTIONEXPl
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LOGIC SYMBOLS4.DIAGRAMATIC SUMMARYI
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lOGIC SYMBOLSWhen RAS goes low, it
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MECHANICAL DATAgeneralElectrical ch
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MECHANICAL DATAceramic packages -ce
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MECHANICAL DATAplastic packages (N
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MECHANICAL DATAceramic chip carrier
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Texas InstrumentsSemiconductor Tech
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TI Sales Offices TI DistributorsALA
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Printed in U.S.A.•TEXASINSTRUMENT
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