1 - Al Kossow's Bitsavers

MOSLSITMS4712816,384·WORD BY 8·BIT READ·ONLY MEMORYJUNE 1983• 16,384 X 8 Organization• Fully Static (No Clocks, No Refresh)• All Inputs and Outputs TTL Compatible• Single 5-V Power Supply• Optional Power Down or Chip Select• 64K Bank Select Option• Maximum Access Time from Address orPower Down:TMS47128-25TMS47128-35TMS47128-45250 ns350 ns450 ns• Worst Case Active Power Dissipation... 330 mW• Worst Case Standby Power Dissipation... 66mWTMS47128 " .. JL OR NL PACKAGEtSTANDARD ROMITOPVIEW)NCVCCA12 52/52A7A13A6ASA5A9A4A11A3 51/51A2A10A1E/E/S3/s3AOQSQ1Q7Q2Q6Q3Q5VssQ4t The package for the bank select ROM is shown on page 2.descriptionThe TMS47128 is a 131 ,072-bit read-only memoryorganized as 16,384 words of 8-bit length. This makesthe TMS47128 ideal for microprocessor basedsystems. The device is fabricated using N-channelsilicon-gate technology for high speed and simple interfacewith bipolar circuits.There are two versions of the TMS47128: the standardROM with options on chip selects and powerdown, and the bank select ROM with similar options.The operation section of this data sheet describes bothversions.PIN NOMENCLATURESTANDARD ROMAO-A13 AddressesE/E/S3/s3 Chip Enable/Power Down or Chip SelectNCNo ConnectionQ1-QS Data Out51/51,52/52 Chip SelectsVCC+5-V SupplyVssGroundThe TMS47128 is fully compatible with Series 74, 74S, or 74LS TTL. The data outputs are three-state for OR-tieingmultiple devices on a common bus. Pins 20, 22, and 27 are mask-programmable, providing additional system flexibility.The data is always available, it is not dependent on external clocking of pins 20, 22, or 27.The TMS47128 is designed for high-density fixed-memory applications such as logic function generation andmicroprogramming. It is pin compatible with Tl's full line of ROMs and EPROMs.This ROM is supplied in 28-pin dual-in-line plastic (NL suffix) or ceramic (JL suffix) packages designed for insertionin mounting-hole rows on 600 mil centers. The device is designed for operation from ooe to 70 0 e.U)Q)t)'S;Q)C~0a:operation, standard ROMaddress (AO-A 13)The address-valid interval determines the device cycle time. The 14-bit positive-logic address is decoded on-chip toselect one of 16,384 words of 8-bit length in the memory array. AO is the least-significant bit and A 13 the mostsignificantbit of the word address.chip select (S1 or S1 and S2 or S2)Pins 22 and 27 can be programmed during mask fabrication to be active with either a high- or a low-level input. WhenPRODUCT PREVIEWThis document contains Information on I product underdevelopment. Texas Instruments re ••.ves the right tochange or discontinue thi' product without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated1'-27