1 - Al Kossow's Bitsavers

MOSLSI, TMS49648192·WORD BY 8·BIT READ·ONLY MEMORYJUNE 1983 - REVISED OCT08ER 1983• 8192 X 8 Organization• Partitioned into Eight 1 K X 8 Pages• Fully Static (No Clocks, No Refresh)• All Inputs and Outputs TTL Compatible• Single 5·V Power Supply• Two Chip-Selects for Flexibility and Power­Down Option• Maximum Access Time from Address... 450 ns• Typical Active Power Dissipation... 275 mW• Available in Chip-on-Board Package AlsodescriptionTMS4964 ... NL PACKAGE(TOP VIEW)A7A6A5VeeA8A9A4 52/S2A3 51/S1A2AlAl0AllAO 0801 Q702 0603 05VSS 04PIN NOMENCLATUREAO - All Addresses01 - 08 Data Out51/S1,52/S2VeeVSSehip Selects+5-V SupplyGroundThe TMS4964 is a 65,536-bit read-only memory organized as 8192 words of 8-bit length. The array is subdividedinto eight 1024 bits x 8 pages. The device is fabricated using N-channel silicon-gate technology for high speed andsimple interface with bipolar circuits.All inputs can be driven directly by Series 74 TTL circuits without the use of any external pull-up resistor. Each outputcan drive two Series 74 or 74S loads without external resistors. The data outputs are three-state for OR-tieing multipledevices on a common bus. Two chip-select controls allow data to be read. These controls are programmable, providingadditional system decode flexibility. The data is always available, it is not dependent on external clocking ofthe control pins.rnQ)(J':;Q)c::?ioa:The TMS4964 is designed for high-density fixed-memory consumer applications.This ROM is supplied in a 24-pin dual-in-line plastic (NL suffix) package designed for insertion in mounting-hole rowson 600-mil centers. It is also available in the chip-on-board package. The device is designed for operation from ooeto 70 o e.operationaddress (AO-A 11 )The address-valid interval determines the device cycle time. The 12-bit positive-logic address is decoded on-chip toselect one of 8192 words of 8-bit length in the memory array. AO is the least-significant bit and A 11 the most-significantbit of the word address. Additionally 24 addresses can generate traps which allow the selection of any 3 of 7 pagesto be active at any point in time. The 8th page is always active. After a write to a pointer register, a normal readcycle must be completed before another write is performed. A normal read is an address outside of the range FEO to FE7.All address changes must be made within 30 ns of when the first address changes to prevent address skewing.chip select/output enable (pins 20 and 21)Each of these pins can be programmed during mask fabrication to be active with either a high or low level input. Whenboth signals are active, all eight outputs are enabled and the eight-bit addressed word can be read. When either signalis not active, all eight outputs are in a high-impedance state.ADVANCE INFORMATIONThis document contains information on 8 new product.Specifications are subject to change without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated7-19