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TMS2732A32,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORYread cycle timingADDRESSESGiVpp01-08standby modeVIHADDRESSESVILVIHEVILVOH01-08VOLXt \'d;'IEI~)--HI~~I»m-0::XJos:cCD
MOSLSITMS276465,536-BI1 ERASABLE PROGRAMMABLE READ-ONLY MEMORYJULY 1983 - REVISED JANUARY 1984• Organization ... 8192 X 8• Single + 5-V Power Supplyo Pin Compatible with TMS2732A EPROMo <strong>Al</strong>l Inputs and Outputs are TTL Compatible• Performance Ranges:TMS2764-20TMS2764-25TMS2764-30TMS2764-35TMS2764-45MAX ACCESSIMIN CYCLE TIME200 ns250 ns300 ns350 ns450 nso Low Active Current ... 100 rnA (Max)o JEOEC Approved Pinouto 21-V Power Supply Required forProgrammingo Fast Programming <strong>Al</strong>gorithmON-Channel Silicon-Gate Technologyo 8-Bit Output for Use in MicroprocessorBased Systems• Static Operation (No Clocks, No RefreshIt Available with MIL-STO-883B Processingand L(O °C to 70°C), E( - 40°C to 85 °C). orM( - 55°C to 125°C) Temperature Rangesin the FuturedescriptionTMS2764 ... JL PACKAGE(TOP VIEW)VPPVCCA12PGMA7NCA6A8A5A9A4A11A3GA2A10A1EAO 0801 Q702 0603 05GND 04PIN NOMENCLATUREAO-A 12 AddressesEChip EnableOutput EnableGGNDNCPGM01-08VCCVPPGroundNo ConnectionProgramoutputs+ 5-V Power Supply+21-V Power SupplyThe TMS2764 is an ultraviolet light-erasable, electrically programmable read-only memory. It has 65,536 bits organizedas 8,192 words of 8-bit length. The TMS2764-20 only requires a single 5-volt power supply with a tolerance of ±5%,and has a maximum access time of 200 ns. This access time is compatible with high-performance microprocessors.The TMS2764 provides two output control lines: Output Enable (G) and Chip Enable {E). This feature allows the Gcontrol line to eliminate bus contention in microprocessor systems. The TMS2764 has a power-down mode that reducesmaximum active current from 100 mA to 35 mA when the device is placed on standby.This EPROM is supplied in a 28-pin, 600-mil dual-in-line ceramic package and is designed for operation from 0 DC to 70 DC.enQ)CJ'S;Q)C~oa:Q.WoperationThe six modes of operation for the TMS2764 are listed in the following table.34ADVANCE INFORMATIONThis document contains Information on 8 new product.Specifications are subject to change without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1984 by Texas Instruments Incorporated6-53
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SMYOOO2.,MOS MemoryData Book1984II
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ALPHANUMERIC INDEX TO DATA SHEETSSM
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TABLE OF CONTENTSALPHANUMERIC INDEX
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MOSLSIRAMs, ROMs, EPROMsSELECTION G
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If you want to give it a try for yo
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INTERCHANGEABILITY GUIDEPART 1 -ALT
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INTERCHANGEABILITY GUIDEFUJITSUMB 8
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INTERCHANGEABILITY GUIDEMOTOROLAMCM
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INTERCHANGEABILITY GUIDETOSHIBATMM
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INTERCHANGEABILITY GUIDESTATIC RAMS
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Alphanumeric Index, Table of Conten
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GLOSSARY fTIMING CONVENTIONS/DATA S
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GLOSSARY/TIMING CONVENTIONS/DATA SH
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GLOSSARY!TIMING CONVENTIONS/DATA SH
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MOSLSITMS411616,384-811 DYNAMIC RAN
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TMS411616,384·811 DYNAMIC RANDOM·
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1MS411616,384-811 DYNAMIC RANDOM-AC
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TMS411616.384·81T DYNAMIC RANDOM·
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zIiADDRESSES~!.....RASCASwDO"*. i,*
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TMS411616,384-81T DYNAMIC RANDOM-AC
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MOSLSITMS416165,536-81T MULTIPORT M
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TMS416165,536-811 MULTIPORT MEMORYf
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TMS416165,536-BIT MULTIPORT MEMORYs
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TMS416165,536-0IT MULTIPORT MEMORYc
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TMS416165,536·BIT MUL TIPORT MEMOR
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TMS416165,536 o BIT MUL TIPORT MEMO
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TMS416165,536·811 MULTIPORT MEMORY
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zI[~~~co,.. twiRL) _,RAS:::~ SI l L
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TMS416165,536·BIT MULTIPORT MEMORY
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~ ___TMS416165.536-BIT MUL TIPORT M
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0>~a~~i'i_';:;Z~~~d~c:::• s:~lTl~
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TMS416165,536-8IT MULTIPORT MEMORY1
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MOSLSITMS4164, SMJ416465,536-8IT DY
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TMS4164, SMJ416465,536-811. DYNAMIC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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SMJ416465,536-81T DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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TMS4164, SMJ416465,536·81T DYNAMIC
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TMS4164, SMJ416465,536·8IT DYNAMIC
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z~~gz~.J:>.c1J
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Z~d~~~~0,'...."CIIICCCD:3of. twIRL)
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MOSLSITMS4256. TMS4257262.144·8IT
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TMS4256, TMS4257262,144·8IT DYNAMI
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TMS4256, TMS4257262,144-8IT DYNAMIC
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TMS4257262.144·8IT DYNAMIC RANDOM
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TMS4256, TMS4257262,144·BIT DYNAMI
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TMS4257262,144·81T DYNAMIC RANDOM
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Z~d~~~~.!..JcoNOTE:'CIIICO(1),- twI
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i:Z~d~~z~+:>0Co ......"CCICCCD:3og.
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MOSLSITMS4416. SMJ441616.384·WORD
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TMS4416, SMJ441616,384·WORD BY 4·
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TMS441616,384-WORD BY 4-BI1 DYNAMIC
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TMS441616,384-WORD BY 4-BIT DYNAMIC
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SMJ441616,384·WORD BY 4·BIT DYNAM
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SMJ441616,384-WORD BY 4-B11 DYNAMIC
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1MS4416, SMJ441616,384·WORD BY 4·
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TMS4416, SMJ441616,384·WORD BY 4·
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z~~~z@towRAs-{rCASAO·A7wDQG:::'.!A
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1:'QltC(()3oc..(()C3~~n_:::Z~~~;;;
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MOSLSITMS446465,536-WORD BY 4-BIT D
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TMS446465,536-WORD 8Y 4-81T DYNAMIC
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TMS446465,536·WORD BY 4·BIT DYNAM
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1MS446465,536·WORD BY 4·B11 DYNAM
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TMS446465,536·WORD BY 4·BIT DYNAM
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RASCAS----{! '.,ReIVIH i~VIL I tRLC
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~~~n_;;;z~~. ~~tTlg ;O~d ;;;t::=z~@
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~Z~~iZ~tw '"[:;-~~~~~:TCDCO ".;:r0~
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MEMORY SUPPORTLSITMS4500ADYNAMIC RA
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TMS4500ADYNAMIC RAM CONTROLLERpin d
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TMS4500ADYNAMIC RAM CONTROLLERarbit
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TMS4500ADYNAMIC RAM CONTROLLERswitc
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TMS4500ADYNAMIC RAM CONTROLLERacces
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TMS4500ADYNAMIC RAM CONTROLLERoutpu
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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TMS4500ADYNAMIC RAM CONTROLLERtypic
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•••••MOSLSI65,536 X 4 Org
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TM4164EC465,536 BY 4·BIT DYNAMIC R
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MOSLSITM4164EL965,536 BY 9·BIT DYN
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TM4164EL965,536 BY 9-BIT DYNAMIC RA
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••••••••0MOSLSI65,5
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TM4164FL865,536 BY 8·BIT DYNAMIC R
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Page 197 and 198: MOSLSITMS2516. SMJ251616.384-BIT ER
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Page 201 and 202: TMS251616,384·BIT ERASABLE PROGRAM
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Page 207 and 208: MOSLSITMS2532, SMJ253232,768·BIT E
Page 211 and 212: TMS253232,768-BI1 ERASABLE PROGRAMM
Page 217 and 218: MOSLSITMS2564, SMJ256465,536-BIT ER
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Page 225 and 226: TMS2564 r SMJ256465 r536-BIT ERASAB
Page 227 and 228: MOSLSITMS2708, TMS27L08, SMJ2708, S
Page 229 and 230: TMS270B, TMS27LOBSMJ270B, SMJ27LOB1
Page 231 and 232: TMS2708. TMS27L081024·WORD BY 8·B
Page 233 and 234: SMJ2708, SMJ27L081024·WORD BY 8·B
Page 235 and 236: TMS2708, TMS27L08SMJ2708, SMJ27L081
Page 237 and 238: MOSLSITMS27162048·WORD BY 8·BIT E
Page 239 and 240: TMS27162048·WORD BY 8·BIT ERASABL
Page 241 and 242: TMS27162048-WORD BY 8-BIT ERASABLEP
Page 243 and 244: TMS2732A32,76B-BIT ERASABLE PROGRAM
Page 245 and 246: TMS2732A32,768-BIT ERASABLE PROGRAM
Page 247: TMS2732A32,768·BIT ERASABLE PROGRA
Page 251 and 252: TMS276465,536·BIT ERASABLE PROGRAM
Page 257 and 258: MOSLSITMS27128131,072·BIT ERASABLE
Page 259 and 260: TMS27128131,072·BI1 ERASABLE PROGR
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Page 265 and 266: Alphanumeric Index, Table of Conten
Page 267 and 268: MOSLSITMS46648192·WORD BY 8·BIT R
Page 269 and 270: TMS46648192·WORD BY 8·BIT READ·O
Page 273 and 274: MOSLSITMS47324096~WORD BY B·BIT RE
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Page 295 and 296: TMS4712816,384·WORD BY 8·BIT READ
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TMS4712816,384·WORD BY 8·BIT READ
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TMS4712816,384-WORD BY 8-BIT READ-O
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MOSLSITMS4725632.768·WORD BY 8·BI
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TMS4725632.768·WORD BY 8·BIT READ
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TMS4725632,768·WORD BY 8·BIT READ
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MOSLSITMS2114, TMS2114L1024·WORD B
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TMS2114, TMS2114L1024·WDRD BY 4·B
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TMS2114. TMS2114L1024·WORD BV 4·B
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ADVANCED MEMORYDEVELOPMENT•Fast A
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TMS2150CACHE ADDRESS COMPARATORabso
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TMS2150CACHE ADDRESS COMPARATORPARA
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MOSLSITMS40162048·WORD BY 8·BIT S
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TMS4016204H-WORD BY H-BIT STATIC RA
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TMS40162048-WDRD BY 8-BIT STATIC RA
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MOSLSITMS4044, TMS40L444096-WORD BY
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TMS4044, TMS40L444096·WORD BY 1·B
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TMS4044, TMS40L444096·WORD BY l·B
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MILITARYCMOSLSISMJ55172048-WORD BY
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SMJ5517204a·WORD BY a·BIT STATIC
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SMJ55172048·WORD BY 8·BIT STATIC
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SMJ55172048-WDRD BY 8-BIT STATIC RA
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SMJ5517204B·WORD BY B·BIT STATIC
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However, the TMS 4164 provides the
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EXPANSION OF 3242 FOR 256-CYCLE REF
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•9-6
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PAD OPENINGIN OVERCOATPADMETALPADME
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Figure 5 shows how the driver outpu
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cpI UO,leWJOJUI suo'le:>!ldd"f\)W(3
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The falling edge of RAS causes R 1
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~--------::~~:~:~~~:--------~~7,34(
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J-Lead AdvantageTexas Instruments P
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Surface Mount Component Availabilit
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fiSECONDARYVAPOR(VAPOR BLANKET)..Fi
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l>'C'2.ri'Q),..o·:::Jen5'....... o
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l>"C'2..(i"Dl...0":=(I)5"....o...3D
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An external refresh counter has bee
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l>'C'CC:)"Q).-+o·::::sen:ro ... ""
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uo!~ew"oJul suo!~ea!ldd"CD .,.., w7
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DOTCLOCKCLOCK ACLOCK C2 xWCLKRAS (A
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B. If dynamic RAM refresh is enable
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•9-38
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The TMS4416/TMS4500A board is arran
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RAS ~CAS \ I2AI \ I '-2BI '-iiD1Ro2
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9-44
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ALEACXRASMAO-MA7CASFIGURE 1 -ALE LE
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The ALE high to ClK low time is giv
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ClKALEACXRASMAO-MA7CASREFREQROY•
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CDinN~1~12 MHzClKINClKOUTWE/iOclKRD
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UO!leWJOJUI SUOlle:ludd"com~'~,i'74
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coen(J)CLOCKWRITEREADROYALEA14-A5MS
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. Access Grant CyclesThe precharge
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whereta(C)tp(BFR)(-103 + tc2 - tp(B
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•9-62
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tt(REH)TCHLLtAEL-RELRAS rise time (
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. Refresh CyclesOn refresh cycles t
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wherethus,fCLKfCLKtCACfCLK[1/2 (tCA
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R/W approach does a normal read-mod
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II(0~""6 MHzI UO!leWJO,ulSUo!le:l!l
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ClKAlE.ACR\ ,----\,\ ,----R/W\ ,---
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4. Row address setup and hold timeT
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CLKrWRITE -------I.~ ..~---REFRESH-
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The read access time on access gran
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implementations in order to relieve
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"C'2..c:rm...o·j(I)....5'o3...mo·
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RELATIVE MEMORY SIZEARCHIVAL STORAG
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increments till satisfied. This pro
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In the example shown in Figure 5, t
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»'C"E..crQ)r+0':::Jtil:;-....o...3
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•9-94
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184LOGIC SYMBOLS1. INTRODUCTIONEXPl
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LOGIC SYMBOLS4.DIAGRAMATIC SUMMARYI
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lOGIC SYMBOLSWhen RAS goes low, it
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MECHANICAL DATAgeneralElectrical ch
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MECHANICAL DATAceramic packages -ce
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MECHANICAL DATAplastic packages (N
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MECHANICAL DATAceramic chip carrier
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Texas InstrumentsSemiconductor Tech
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TI Sales Offices TI DistributorsALA
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Printed in U.S.A.•TEXASINSTRUMENT
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