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1MS251616.384-BI1 ERASABLE PROGRAMMABLE READ-ONLY MEMORIESrecommended operating conditionsPARAMETERTMS2516-35TMS2516-45MIN NOM MAX MIN NOM MAXSupply voltage, VCC (see Note 2) 4.75 5 5.25 4.75 5 5.25 VSupply voltage, Vpp (see Note 3) VCC VCC VSupply voltage, VSS 0 0 VHigh-level input voltage, VIH 2 VCC+ 1 2 VCC+ 1 VLow-level input voltage, VIL -0.1 0.8 -0.1 0.8 VRead cycle time, tc(rd) 350 450 nsOperating free-air temperature, T A 0 70 0 70 °cUNITNOTES:2. Vee must be applied before or at the same time· as Vpp and removed after or at the same time as Vpp. The device must not be inserted intoor removed from the board when Vpp or Vee is applied.3. Vpp can be connected to Vee directly (except in the program mode). Vee supply current in this case would be ICC + Ipp. During programming.Vpp must be maintained at 25 V (± 1 V).electrical characteristics over full ranges of recommended operating conditionsm"'0~PARAMETER(active)o3: t Typical values are at T A = 25°C and nominal voltages.cCD
TMS251616,384·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORIESswitching characteristics over full ranges of recommended operating conditions (see Note 4)PARAMETERTEST CONDITIONS TMS2516-35 TMS2516-45(SEE NOTES 4 AND 5) MIN Typt MAX MIN Typt MAXtalA) Access time from address 250 350 280talS) Access time from chip select 120talPR) Access time from PD/PGM 250 350 280Output data valid aftertv(A)address changeCL = 100 pF,0 0tdislS)Output disable time from chipselect during read onlyiOutput disable time from chip1 Series 74 TTL load,trS 20 ns,tfs20 ns0 100 0tdislS) select during program 120and program verify itdislPR)Output disable timefrom PD/PGM i0 100450150450100120100UNITnsnsnsnsnsnsnst <strong>Al</strong>l typical values are at T A = 25°C and nominal voltages.~ Value calculated from 0.5 volt delta to measured output level.recommended timing requirements for programming T A 25°C (see Note 4)TMS2516PARAMETERMIN Typt MAXtw(PR) Pulse duration, program pulse 955trlPR) Rise time, program pulse 5tflPR) Fall time, program pulse 5tsulA) Address setup time 2tsulS) Chip-select setup time 2tsulD) Data setup time 2tsulVPP) Setup time from Vpp 0thlA) Address hold time 2thiS) Chip-select hold time 2thlD) Data hold time 2t Typical values are at nominal voltages.NOTES: 4. Timing measurement reference levels: inputs O.B V and 2 V, outputs 0.65 V and 2.2 V.5. Common test conditions apply for tdis except during programming. For talA). taIS), and tdis' PDIPGM = S = VIL'UNITmsnsnsflsflSflsnsflSflSflsCI)Q)(.)'S;Q)C~oa::a..w4TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-5
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SMYOOO2.,MOS MemoryData Book1984II
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ALPHANUMERIC INDEX TO DATA SHEETSSM
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TABLE OF CONTENTSALPHANUMERIC INDEX
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MOSLSIRAMs, ROMs, EPROMsSELECTION G
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If you want to give it a try for yo
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INTERCHANGEABILITY GUIDEPART 1 -ALT
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INTERCHANGEABILITY GUIDEFUJITSUMB 8
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INTERCHANGEABILITY GUIDEMOTOROLAMCM
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INTERCHANGEABILITY GUIDETOSHIBATMM
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INTERCHANGEABILITY GUIDESTATIC RAMS
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Alphanumeric Index, Table of Conten
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GLOSSARY fTIMING CONVENTIONS/DATA S
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GLOSSARY/TIMING CONVENTIONS/DATA SH
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GLOSSARY!TIMING CONVENTIONS/DATA SH
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MOSLSITMS411616,384-811 DYNAMIC RAN
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TMS411616,384·811 DYNAMIC RANDOM·
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1MS411616,384-811 DYNAMIC RANDOM-AC
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TMS411616.384·81T DYNAMIC RANDOM·
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zIiADDRESSES~!.....RASCASwDO"*. i,*
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TMS411616,384-81T DYNAMIC RANDOM-AC
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MOSLSITMS416165,536-81T MULTIPORT M
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TMS416165,536-811 MULTIPORT MEMORYf
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TMS416165,536-BIT MULTIPORT MEMORYs
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TMS416165,536-0IT MULTIPORT MEMORYc
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TMS416165,536·BIT MUL TIPORT MEMOR
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TMS416165,536 o BIT MUL TIPORT MEMO
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TMS416165,536·811 MULTIPORT MEMORY
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zI[~~~co,.. twiRL) _,RAS:::~ SI l L
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TMS416165,536·BIT MULTIPORT MEMORY
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~ ___TMS416165.536-BIT MUL TIPORT M
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0>~a~~i'i_';:;Z~~~d~c:::• s:~lTl~
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TMS416165,536-8IT MULTIPORT MEMORY1
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MOSLSITMS4164, SMJ416465,536-8IT DY
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TMS4164, SMJ416465,536-811. DYNAMIC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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SMJ416465,536-81T DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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TMS4164, SMJ416465,536·81T DYNAMIC
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TMS4164, SMJ416465,536·8IT DYNAMIC
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z~~gz~.J:>.c1J
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Z~d~~~~0,'...."CIIICCCD:3of. twIRL)
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MOSLSITMS4256. TMS4257262.144·8IT
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TMS4256, TMS4257262,144·8IT DYNAMI
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TMS4256, TMS4257262,144-8IT DYNAMIC
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TMS4257262.144·8IT DYNAMIC RANDOM
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TMS4256, TMS4257262,144·BIT DYNAMI
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TMS4257262,144·81T DYNAMIC RANDOM
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Z~d~~~~.!..JcoNOTE:'CIIICO(1),- twI
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i:Z~d~~z~+:>0Co ......"CCICCCD:3og.
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MOSLSITMS4416. SMJ441616.384·WORD
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TMS4416, SMJ441616,384·WORD BY 4·
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TMS441616,384-WORD BY 4-BI1 DYNAMIC
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TMS441616,384-WORD BY 4-BIT DYNAMIC
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TMS441616,384-WORD BY 4-BIT DYNAMIC
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SMJ441616,384·WORD BY 4·BIT DYNAM
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SMJ441616,384-WORD BY 4-B11 DYNAMIC
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1MS4416, SMJ441616,384·WORD BY 4·
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TMS4416, SMJ441616,384·WORD BY 4·
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z~~~z@towRAs-{rCASAO·A7wDQG:::'.!A
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1:'QltC(()3oc..(()C3~~n_:::Z~~~;;;
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MOSLSITMS446465,536-WORD BY 4-BIT D
Page 149 and 150: TMS446465,536-WORD 8Y 4-81T DYNAMIC
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Page 157 and 158: TMS446465,536-WORD BY 4-BIT DYNAMIC
Page 159 and 160: RASCAS----{! '.,ReIVIH i~VIL I tRLC
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Page 163 and 164: ~Z~~iZ~tw '"[:;-~~~~~:TCDCO ".;:r0~
Page 165 and 166: MEMORY SUPPORTLSITMS4500ADYNAMIC RA
Page 167 and 168: TMS4500ADYNAMIC RAM CONTROLLERpin d
Page 169 and 170: TMS4500ADYNAMIC RAM CONTROLLERarbit
Page 171 and 172: TMS4500ADYNAMIC RAM CONTROLLERswitc
Page 173 and 174: TMS4500ADYNAMIC RAM CONTROLLERacces
Page 175 and 176: TMS4500ADYNAMIC RAM CONTROLLERoutpu
Page 177 and 178: TMS4500ADYNAMIC RAM CONTROLLERtypic
Page 179 and 180: TMS4500ADYNAMIC RAM CONTROLLERtypic
Page 181 and 182: Alphanumeric Index, Table of Conten
Page 183 and 184: •••••MOSLSI65,536 X 4 Org
Page 185 and 186: TM4164EC465,536 BY 4·BIT DYNAMIC R
Page 187 and 188: MOSLSITM4164EL965,536 BY 9·BIT DYN
Page 189 and 190: TM4164EL965,536 BY 9-BIT DYNAMIC RA
Page 191 and 192: ••••••••0MOSLSI65,5
Page 193 and 194: TM4164FL865,536 BY 8·BIT DYNAMIC R
Page 195 and 196: Alphanumeric Index, Table of Conten
Page 197 and 198: MOSLSITMS2516. SMJ251616.384-BIT ER
Page 199: TMS2516, SMJ251616,384-BIT ERASABLE
Page 203 and 204: SMJ251616,384-BIT ERASABLE PROGRAMM
Page 205 and 206: o 441MS2516, SMJ251616,384·B11 ERA
Page 207 and 208: MOSLSITMS2532, SMJ253232,768·BIT E
Page 209 and 210: TMS2532, SMJ253232,768-BIT ERASABLE
Page 211 and 212: TMS253232,768-BI1 ERASABLE PROGRAMM
Page 217 and 218: MOSLSITMS2564, SMJ256465,536-BIT ER
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Page 225 and 226: TMS2564 r SMJ256465 r536-BIT ERASAB
Page 227 and 228: MOSLSITMS2708, TMS27L08, SMJ2708, S
Page 229 and 230: TMS270B, TMS27LOBSMJ270B, SMJ27LOB1
Page 231 and 232: TMS2708. TMS27L081024·WORD BY 8·B
Page 233 and 234: SMJ2708, SMJ27L081024·WORD BY 8·B
Page 235 and 236: TMS2708, TMS27L08SMJ2708, SMJ27L081
Page 237 and 238: MOSLSITMS27162048·WORD BY 8·BIT E
Page 239 and 240: TMS27162048·WORD BY 8·BIT ERASABL
Page 241 and 242: TMS27162048-WORD BY 8-BIT ERASABLEP
Page 243 and 244: TMS2732A32,76B-BIT ERASABLE PROGRAM
Page 245 and 246: TMS2732A32,768-BIT ERASABLE PROGRAM
Page 247 and 248: TMS2732A32,768·BIT ERASABLE PROGRA
Page 249 and 250: MOSLSITMS276465,536-BI1 ERASABLE PR
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TMS276465,536·BIT ERASABLE PROGRAM
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TMS276465,536-BIT ERASABLE PROGRAMM
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TMS276465,536-BIT ERASABLE PROGRAMM
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MOSLSITMS27128131,072·BIT ERASABLE
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TMS27128131,072·BI1 ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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MOSLSITMS46648192·WORD BY 8·BIT R
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TMS46648192·WORD BY 8·BIT READ·O
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MOSLSITMS47324096~WORD BY B·BIT RE
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MOSLSITMS47648192·WORD BY 8·BIT R
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MOSLSI, TMS49648192·WORD BY 8·BIT
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MOSLSITMS4712816,384·WORD BY 8·BI
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TMS4712816,384·WORD BY 8·BIT READ
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TMS4712816,384-WORD BY 8-BIT READ-O
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MOSLSITMS4725632.768·WORD BY 8·BI
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TMS4725632.768·WORD BY 8·BIT READ
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MOSLSITMS2114, TMS2114L1024·WORD B
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TMS2114, TMS2114L1024·WDRD BY 4·B
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TMS2114. TMS2114L1024·WORD BV 4·B
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ADVANCED MEMORYDEVELOPMENT•Fast A
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TMS2150CACHE ADDRESS COMPARATORabso
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TMS2150CACHE ADDRESS COMPARATORPARA
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MOSLSITMS40162048·WORD BY 8·BIT S
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TMS4016204H-WORD BY H-BIT STATIC RA
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TMS40162048-WDRD BY 8-BIT STATIC RA
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MOSLSITMS4044, TMS40L444096-WORD BY
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TMS4044, TMS40L444096·WORD BY 1·B
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TMS4044, TMS40L444096·WORD BY l·B
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MILITARYCMOSLSISMJ55172048-WORD BY
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SMJ5517204a·WORD BY a·BIT STATIC
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SMJ55172048·WORD BY 8·BIT STATIC
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SMJ55172048-WDRD BY 8-BIT STATIC RA
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SMJ5517204B·WORD BY B·BIT STATIC
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However, the TMS 4164 provides the
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EXPANSION OF 3242 FOR 256-CYCLE REF
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•9-6
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PAD OPENINGIN OVERCOATPADMETALPADME
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Figure 5 shows how the driver outpu
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cpI UO,leWJOJUI suo'le:>!ldd"f\)W(3
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The falling edge of RAS causes R 1
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~--------::~~:~:~~~:--------~~7,34(
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J-Lead AdvantageTexas Instruments P
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Surface Mount Component Availabilit
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fiSECONDARYVAPOR(VAPOR BLANKET)..Fi
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l>'C'2.ri'Q),..o·:::Jen5'....... o
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l>"C'2..(i"Dl...0":=(I)5"....o...3D
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An external refresh counter has bee
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l>'C'CC:)"Q).-+o·::::sen:ro ... ""
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uo!~ew"oJul suo!~ea!ldd"CD .,.., w7
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DOTCLOCKCLOCK ACLOCK C2 xWCLKRAS (A
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B. If dynamic RAM refresh is enable
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•9-38
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The TMS4416/TMS4500A board is arran
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RAS ~CAS \ I2AI \ I '-2BI '-iiD1Ro2
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9-44
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ALEACXRASMAO-MA7CASFIGURE 1 -ALE LE
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The ALE high to ClK low time is giv
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ClKALEACXRASMAO-MA7CASREFREQROY•
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CDinN~1~12 MHzClKINClKOUTWE/iOclKRD
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UO!leWJOJUI SUOlle:ludd"com~'~,i'74
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coen(J)CLOCKWRITEREADROYALEA14-A5MS
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. Access Grant CyclesThe precharge
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whereta(C)tp(BFR)(-103 + tc2 - tp(B
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•9-62
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tt(REH)TCHLLtAEL-RELRAS rise time (
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. Refresh CyclesOn refresh cycles t
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wherethus,fCLKfCLKtCACfCLK[1/2 (tCA
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R/W approach does a normal read-mod
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II(0~""6 MHzI UO!leWJO,ulSUo!le:l!l
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ClKAlE.ACR\ ,----\,\ ,----R/W\ ,---
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4. Row address setup and hold timeT
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CLKrWRITE -------I.~ ..~---REFRESH-
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The read access time on access gran
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implementations in order to relieve
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"C'2..c:rm...o·j(I)....5'o3...mo·
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RELATIVE MEMORY SIZEARCHIVAL STORAG
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increments till satisfied. This pro
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In the example shown in Figure 5, t
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»'C"E..crQ)r+0':::Jtil:;-....o...3
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•9-94
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184LOGIC SYMBOLS1. INTRODUCTIONEXPl
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LOGIC SYMBOLS4.DIAGRAMATIC SUMMARYI
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lOGIC SYMBOLSWhen RAS goes low, it
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MECHANICAL DATAgeneralElectrical ch
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MECHANICAL DATAceramic packages -ce
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MECHANICAL DATAplastic packages (N
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MECHANICAL DATAceramic chip carrier
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Texas InstrumentsSemiconductor Tech
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TI Sales Offices TI DistributorsALA
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Printed in U.S.A.•TEXASINSTRUMENT
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