1 - Al Kossow's Bitsavers

TMS4500ADYNAMIC RAM CONTROLLERoutput tristate timingOUTPUTSrefresh cycle timing(three cycle)refresh cycle timing(four cycle)\;-'CAV-CEL(I)(1)(,)'S;(1)c......0C.C.:len... >0E(1).~'t:JCCO~«a:(,)'ECOc>C~lMAVARl~t On the access grant cycle following refresh, the occurrence of CAS low depends on the relative occurrence of ALE low to ACX low. If ACX occurs priorto or coincident with ALE then CAS and address mUltiplexing are timed from the ClK high transition with tREl-MAX delay from RAs low to address notvalid. If ACX occurs 20 ns or more after ALE, then CAS and address multiplexing are timed from the ClK low transition.84TEXAS INSTRUMENTS4-135INCORPORATED