1 - Al Kossow's Bitsavers

TMS4500ADYNAMIC RAM CONTROLLERswitching chara~teristics over recommended supply voltage range and operating ambient temperature range(see Figure 1)tAEl-RElPARAMETERTime delay, ALE low toRAS starting lowTESTTMS4500A-15 TMS4500A-20 TMS4500A-25CONDITIONS MIN MAX MIN MAX MIN MAX30 40 50tt(REl) RAS fall time 15 20 25Cl = 160pFTime delay, row address validtRAV-MAV40 50 60to memory address validtAEH-MAVtAEl-RYltAEl-CElTime delay, ALE high tovalid memory addressTime delay, ALE to ROY start.inglow (TWST = 1 or refresh in progress)Time delay, ALE low to CASstarting low55 70 90Cl = 40 pF 20 25 3560 150 75 200 100 250Time delay, ALE high to RAStAEH-REH25 3040starting highCl = 160pFttIMAV) Address transition time 15 20 25tACl-MAX Row address hold from ACX low 15 20 25Time delay, memory addresstMAV-CElvalid to CAS starting low0 0 0ttlCELl CAS fall time Cl = 320 pF 15 20 25Time delay, ACX low to CAS'tACl-CElstarting low50 90 65 130 85 165tACH-REHTime delay, ACX to RASstarting highCl = 160 pF30 40 50ttIREH) RAS rise time 15 20 25Time delay, ACX high to CAStACH-CEHstarting high5 30 10 40 15 50ttICEH) CAS rise time Cl =320 pF 30 35 45Column address hold fromtACH-MAXACX highCl = 160 pF 15 20 25tCH-RYHtRFl-RFltCH-RFltCl-MAVtCH-RRltMAV-RRltCl-RFHtCH-RFHtCH-RRHtCH-MAXTime delay, ClK high to ROY startinghigh lafter AcX low) Isee Note 9)Time delay, REFREO external tillsupported by REFREO internalTime delay, ClK high till REFREOinternal starting lowTime delay, ClK low till refreshaddress validTime delay, ClK high tillrefresh RAS starting lowTime delay, refresh addressvalid till refresh RAS lowTime delay, ClK low to REF REOstarting high 13 cycle refresh)Time delay, ClK high to REFREOstarting high 14 cycle refresh)Time delay, ClK high to refreshRAS starting highTime delay, refresh address holdafter ClK high.Cl = 40 pF 35 45 60Cl = 40 pF25 30 3030 35 4575 100 12510 50 15 60 20 805 5 5Cl = 160pF 45 55 7545 55 755 35 10 45 10 6015 20 25UNITnsrJ)Q)(.)'>Q)C.....oa.a.::::Jen>...oEQ)~"Cc:CO~«a:(.)'ECOc:>CNOTE 9: ROY returns high on the rising edge of ClK. If TWST = 0, then on an access grant cycle ROY goes high on the same edge that causes access RASlow. If TWST = 1, then ROY goes to the high level on the first rising ClK edge after ACx goes low on access cycles and on the next rising edgeafter the edge that causes access RAS low on access grant cycles (assuming ACX low).34TEXAS INSTRUMENTS 4-131INCORPORATED