1 - Al Kossow's Bitsavers

TMS4500ADYNAMIC RAM CONTROLLERpin descriptions (continued)CSInputChip Select - A low on this input enables an access cycle. The trailing edge ofALE latches the chip select input.REN1INPUTRAS Enable 1 - This input is used to select one of two banks of RAM via theRASO and RAS1 outputs when chip select is present. When it is low, RASO isselected; when it is high, RAS1 is selected.InputAccess Control, Read; Access Control, Write - A low on either of these inputscauses the column address to appear on MAO - MA7 and the column addressstrobe. The rising edge of ACR or ACW terminates the cycle by ending RAS andCAS strobes. When ACR and ACW are both low, MAO - MA7, RASa, RAS1, andCAS go into a high-impedance (floating) state.ClKInputSystem Clock - This input provides the master timing to generate refresh cycletimings and refresh rate. Refres.h rate is determined by the TWST, FS1, FSOinputs.RASO, RAS1CASROYTWSTFSO, FS1I nput/OutputOutputOutputOutputInputInputsRefresh Request - (This input should be driven by an open-collector output.)On input, a low·going edge initiates a refresh cycle and will cause the internalrefresh timer to be reset on the next falling edge of the ClK. As an output, alow-going edge signals an internal refresh request and that the refresh timer willbe reset on the next low-going edge of ClK. REF REO will remain low until therefresh cycle is in progress and the current refresh address is present on MAO-MA7 .(Note: REFREO contains an internal pull-up resistor with a nominal resistanceof 10 kilohms.)Row Address Strobe - These three-state outputs are used to latch the row addressinto the bank of DRAMs selected by REN1. On refresh both signals are driven.Column Address Strobe - This three-state output is used to latch the columnaddress into the DRAM array.Ready - This totem-pole output synchronizes memories that are too slow toguarantee microprocessor access time requirements. This output is also used toinhibit access cycles during refresh when in cycle-steal mode.TiminglWait Strap - A high on this input indicates a wait state should be addedto each memory cycle. In addition it is used in conjunction with FSO and FS1 todetermine refresh rate and timing.Frequency Select 0; Frequency Select 1 - These are strap inputs to select Modeand Frequency of operation as shown in Table 1.(I)Q)U'S;Q)C......oc.C.::JCJ)...>oEQ)2"CCCO2«a:u'ECOc>C14TEXAS INSTRUMENTS 4-127INCORPORATED