1 - Al Kossow's Bitsavers

1MS446465,536·WORD BY 4·B11 DYNAMIC RAMtiming requirements over recommended supply voltage range and operating free-air temperature rangeALT. TMS4464-10 TMS4464-12. PARAMETER UNITSYMBOL MIN MAX MIN MAXtc(P) Page mode cycle time tpc 110 130 nstc(PM) Page-mode cycle time (read-modify-write cycle) tpCM 180 210 nstc(rd) Read cycle time t tRC 200 230 nstc(W) Write cycle time twc 200 230 nstc(rdW) Read-write/read-modify-write cycle time tRWC 270 310 nstw(CH)P Pulse duration, CAS high (page mode) tcp 40 50 nstw(CH) Pulse duration, CAS high (non-page mode) tCPN 40 50 nstw(CL) Pulse duration, CAS low:!: tCAS 60 10,000 70 10,000 nstw!RH) Pulse duration, RAS high (precharge time) tRP 90 100 nstWIRL) Pulse duration, RAS low§ tRAS 100 10,000 120 10,000 nstw(W) Write pulse duration twp 35 40 nstt Transition times (rise and fall) for RAS and CAS tT 3 50 3 50 nstsu(CA) Column address setup time tASC 0 0 nstsu(RA) Row address setup time tASR 0 0 nstsu(D) Data setup time tDS 0 0 nstsu(rd) Read command setup time tRCS 0 0 nsEarly write command setuptsu(WCUtime before CAS lowtwcs 0 0nstsu(WCH) Write command setup time before CAS high tCWL 30 40 nstsu(WRH) Write command setup time before RAS high tRWL 30 40 nsth(CLCA) Column address hold time after CAS low tCAH 20 20 nsth(RA) Row address hold time tRAH 15 15 nsth(RLCA) Column address hold time after RAS low tAR 60 70 nsth(CLD) Data hold time after CAS low tDH 30 35 nsth(RLD) Data hold time after RAS low tDHR 70 85 nsth(WLDI Data hold time after W low tDH 30 35 nsth(CHrd) Read command hold time after CAS high tRCH 0 0 nsth(RHrd) Read command hold time after RAS high tRRH 10 10 nsth(CLW) Write command hold time after CAS low tWCH 30 35 nsth(RLW) Write command hold time after RAS low tWCR 70 85 nstRLCHR Delay time, RAS low to CAS high' tCHR 20 25 nstRLCH Delay time, RAS low to CAS high tCSH 100 120 nstCHRL Delay time, CAS high to RAS low tCRP 0 0 nstCLRH Delay time, CAS low to RAS high tRSH 60 70 nstCLWLDelay time, CAS low to W low(read-modify-write cycle only)#tCWD 95 105 ns'tCLRL Delay time, CAS low to RAS low' tCSR 20 25 nsDelay time, RAS low to CAS lowtRLCL (maximum value specified only tRCD 25 40 25 50 nsto guarantee access time)tRLWLDelay time, RAS low to W low(read-modify-write cycle only)#tRWD 135 155 nstGHDDelay time, G high beforedata applied at DQtGDD 30 30trf Refresh time interval tREF 4 4 mst All cycle times assume tt ~ 5 ns.~ In a read-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional CAS low time(tw(CL))'§ In a read-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional RAs low time~RL))', CAS-before-l'fAS refresh option only./I G must disable the output buffers prior to applying data to the device.nsCI)Q)(.)':;:Q)C..."-oc.C.:::len>"-oEQ):2:"Cs:::ca:2: