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TMS4416, SMJ441616,384·WORD BY 4·BIT DYNAMIC RAMRAS-only refresh timingRASI. tc(rd) -I. I IVIH --------------:111' I'W'RLI~J= ~VIL N- -:fi i"----IIl~tw(RH)~---..t t4- ttI III~l4-tt. 'II I .. I ~AO·A7Q)~Cos:(t)3o ...
MOSLSITMS446465,536-WORD BY 4-BIT DYNAMIC RAMNOVEMBER 19B3 - REVISED JANUARY 1984• 65,536 X 4 Organization• Single +5-V Supply (10% Tolerance)• JEDEC Standardized Pin-Out• Pin-Out Identical to TMS4416(16K X 4 Dynamic RAM)• Performance Ranges:DEVICEACCESSTIMEROWADDRESS(MAX)ACCESSTIMECOLUMNADDRESS(MAX)READORWRITECYCLE(MIN)READ-MODIFY-WRITECYCLE(MIN)TMS4464 ... JL OR NL PACKAGE(TOP VIEW)GDOlVSSDQ4CASDQ3AD<strong>Al</strong>A2A3A7TMS4464-10TMS4464-12TMS4464-15TMS4464-20100 ns120 ns150 ns200 ns60 ns70 ns85 ns12d ns200 ns230 ns260 ns330 ns270 ns310 ns345 ns435 ns• Long Refresh Period ... 4 ms (MAX)• Low Refresh Overhead Time ... As Low As 1.3% of TotalRefresh Period• On-Chip Substrate Bias Generator• <strong>Al</strong>l Inputs, Outputs, and Clocks Fully TTL Compatible• 3-State Unlatched Output• Early Write or G to Control Output Buffer Impedance• Page-Mode Operation for Faster Access• Power Dissipation As Low As:Operating ... 250 mW (TVP)Standby ... 12.5 mW (TVP)• RAS-Only Refresh Mode• Hidden Refresh Mode• CAS-Before-RAS Refresh Mode (Optional)descriptionPIN NOMENCLATUREAO·A7Address InputsCASColumn Address StrobeD01·D04 Data·ln/Data·OutGOutput EnableRASRow Address StrobeVDD+5-V SupplyVSSGroundINWrite EnableThe TMS4464 is a high-speed, 262, 144-bit dynamic random-access memory, organized as 65,536 words of fourbits each. It employs state-of-the-art SMOS (scaled MOS) N-channel double-level polysilicon gate technology for veryhigh performance combined with low cost and improved reliability.rnQ)Co)·SQ)c....o0.0.::::1(J)...>-oEQ)~"Ct:ca::?E
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SMYOOO2.,MOS MemoryData Book1984II
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ALPHANUMERIC INDEX TO DATA SHEETSSM
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TABLE OF CONTENTSALPHANUMERIC INDEX
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MOSLSIRAMs, ROMs, EPROMsSELECTION G
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If you want to give it a try for yo
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INTERCHANGEABILITY GUIDEPART 1 -ALT
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INTERCHANGEABILITY GUIDEFUJITSUMB 8
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INTERCHANGEABILITY GUIDEMOTOROLAMCM
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INTERCHANGEABILITY GUIDETOSHIBATMM
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INTERCHANGEABILITY GUIDESTATIC RAMS
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Alphanumeric Index, Table of Conten
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GLOSSARY fTIMING CONVENTIONS/DATA S
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GLOSSARY/TIMING CONVENTIONS/DATA SH
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GLOSSARY!TIMING CONVENTIONS/DATA SH
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MOSLSITMS411616,384-811 DYNAMIC RAN
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TMS411616,384·811 DYNAMIC RANDOM·
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1MS411616,384-811 DYNAMIC RANDOM-AC
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TMS411616.384·81T DYNAMIC RANDOM·
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zIiADDRESSES~!.....RASCASwDO"*. i,*
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TMS411616,384-81T DYNAMIC RANDOM-AC
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MOSLSITMS416165,536-81T MULTIPORT M
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TMS416165,536-811 MULTIPORT MEMORYf
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TMS416165,536-BIT MULTIPORT MEMORYs
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TMS416165,536-0IT MULTIPORT MEMORYc
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TMS416165,536·BIT MUL TIPORT MEMOR
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TMS416165,536 o BIT MUL TIPORT MEMO
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TMS416165,536·811 MULTIPORT MEMORY
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zI[~~~co,.. twiRL) _,RAS:::~ SI l L
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TMS416165,536·BIT MULTIPORT MEMORY
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~ ___TMS416165.536-BIT MUL TIPORT M
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0>~a~~i'i_';:;Z~~~d~c:::• s:~lTl~
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TMS416165,536-8IT MULTIPORT MEMORY1
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MOSLSITMS4164, SMJ416465,536-8IT DY
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TMS4164, SMJ416465,536-811. DYNAMIC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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TMS416465,536-811 DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
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SMJ416465,536-81T DYNAMIC RANDOM-AC
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SMJ416465,536-011 DYNAMIC RANDOM-AC
Page 95 and 96: TMS4164, SMJ416465,536·81T DYNAMIC
Page 97 and 98: TMS4164, SMJ416465,536·8IT DYNAMIC
Page 99 and 100: z~~gz~.J:>.c1J
Page 101 and 102: Z~d~~~~0,'...."CIIICCCD:3of. twIRL)
Page 103 and 104: MOSLSITMS4256. TMS4257262.144·8IT
Page 105 and 106: TMS4256, TMS4257262,144·8IT DYNAMI
Page 107 and 108: TMS4256, TMS4257262,144-8IT DYNAMIC
Page 111 and 112: TMS4257262.144·8IT DYNAMIC RANDOM
Page 113 and 114: TMS4256, TMS4257262,144·BIT DYNAMI
Page 117 and 118: TMS4257262,144·81T DYNAMIC RANDOM
Page 119 and 120: Z~d~~~~.!..JcoNOTE:'CIIICO(1),- twI
Page 121 and 122: i:Z~d~~z~+:>0Co ......"CCICCCD:3og.
Page 125 and 126: MOSLSITMS4416. SMJ441616.384·WORD
Page 127 and 128: TMS4416, SMJ441616,384·WORD BY 4·
Page 129 and 130: TMS441616,384-WORD BY 4-BI1 DYNAMIC
Page 131 and 132: TMS441616,384-WORD BY 4-BIT DYNAMIC
Page 135 and 136: SMJ441616,384·WORD BY 4·BIT DYNAM
Page 137 and 138: SMJ441616,384-WORD BY 4-B11 DYNAMIC
Page 139 and 140: 1MS4416, SMJ441616,384·WORD BY 4·
Page 141 and 142: TMS4416, SMJ441616,384·WORD BY 4·
Page 143 and 144: z~~~z@towRAs-{rCASAO·A7wDQG:::'.!A
Page 145: 1:'QltC(()3oc..(()C3~~n_:::Z~~~;;;
Page 149 and 150: TMS446465,536-WORD 8Y 4-81T DYNAMIC
Page 151 and 152: TMS446465,536·WORD BY 4·BIT DYNAM
Page 153 and 154: 1MS446465,536·WORD BY 4·B11 DYNAM
Page 155 and 156: TMS446465,536·WORD BY 4·BIT DYNAM
Page 159 and 160: RASCAS----{! '.,ReIVIH i~VIL I tRLC
Page 161 and 162: ~~~n_;;;z~~. ~~tTlg ;O~d ;;;t::=z~@
Page 163 and 164: ~Z~~iZ~tw '"[:;-~~~~~:TCDCO ".;:r0~
Page 165 and 166: MEMORY SUPPORTLSITMS4500ADYNAMIC RA
Page 167 and 168: TMS4500ADYNAMIC RAM CONTROLLERpin d
Page 169 and 170: TMS4500ADYNAMIC RAM CONTROLLERarbit
Page 171 and 172: TMS4500ADYNAMIC RAM CONTROLLERswitc
Page 173 and 174: TMS4500ADYNAMIC RAM CONTROLLERacces
Page 175 and 176: TMS4500ADYNAMIC RAM CONTROLLERoutpu
Page 177 and 178: TMS4500ADYNAMIC RAM CONTROLLERtypic
Page 179 and 180: TMS4500ADYNAMIC RAM CONTROLLERtypic
Page 181 and 182: Alphanumeric Index, Table of Conten
Page 183 and 184: •••••MOSLSI65,536 X 4 Org
Page 185 and 186: TM4164EC465,536 BY 4·BIT DYNAMIC R
Page 187 and 188: MOSLSITM4164EL965,536 BY 9·BIT DYN
Page 189 and 190: TM4164EL965,536 BY 9-BIT DYNAMIC RA
Page 191 and 192: ••••••••0MOSLSI65,5
Page 193 and 194: TM4164FL865,536 BY 8·BIT DYNAMIC R
Page 195 and 196: Alphanumeric Index, Table of Conten
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MOSLSITMS2516. SMJ251616.384-BIT ER
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TMS2516, SMJ251616,384-BIT ERASABLE
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TMS251616,384·BIT ERASABLE PROGRAM
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SMJ251616,384-BIT ERASABLE PROGRAMM
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o 441MS2516, SMJ251616,384·B11 ERA
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MOSLSITMS2532, SMJ253232,768·BIT E
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TMS253232,768-BI1 ERASABLE PROGRAMM
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MOSLSITMS2564, SMJ256465,536-BIT ER
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TMS256465,536-BIT ERASABLE PROGRAMM
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TMS2564 r SMJ256465 r536-BIT ERASAB
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MOSLSITMS2708, TMS27L08, SMJ2708, S
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TMS270B, TMS27LOBSMJ270B, SMJ27LOB1
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TMS2708. TMS27L081024·WORD BY 8·B
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SMJ2708, SMJ27L081024·WORD BY 8·B
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TMS2708, TMS27L08SMJ2708, SMJ27L081
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MOSLSITMS27162048·WORD BY 8·BIT E
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TMS27162048·WORD BY 8·BIT ERASABL
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TMS27162048-WORD BY 8-BIT ERASABLEP
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TMS2732A32,76B-BIT ERASABLE PROGRAM
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TMS2732A32,768-BIT ERASABLE PROGRAM
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TMS2732A32,768·BIT ERASABLE PROGRA
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MOSLSITMS276465,536-BI1 ERASABLE PR
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TMS276465,536·BIT ERASABLE PROGRAM
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MOSLSITMS27128131,072·BIT ERASABLE
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TMS27128131,072·BI1 ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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TMS27128131,072·BIT ERASABLE PROGR
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MOSLSITMS46648192·WORD BY 8·BIT R
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TMS46648192·WORD BY 8·BIT READ·O
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MOSLSITMS47324096~WORD BY B·BIT RE
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MOSLSITMS47648192·WORD BY 8·BIT R
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MOSLSI, TMS49648192·WORD BY 8·BIT
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MOSLSITMS4712816,384·WORD BY 8·BI
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TMS4712816,384·WORD BY 8·BIT READ
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TMS4712816,384-WORD BY 8-BIT READ-O
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MOSLSITMS4725632.768·WORD BY 8·BI
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TMS4725632.768·WORD BY 8·BIT READ
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MOSLSITMS2114, TMS2114L1024·WORD B
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TMS2114, TMS2114L1024·WDRD BY 4·B
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TMS2114. TMS2114L1024·WORD BV 4·B
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ADVANCED MEMORYDEVELOPMENT•Fast A
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TMS2150CACHE ADDRESS COMPARATORabso
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TMS2150CACHE ADDRESS COMPARATORPARA
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MOSLSITMS40162048·WORD BY 8·BIT S
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TMS4016204H-WORD BY H-BIT STATIC RA
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TMS40162048-WDRD BY 8-BIT STATIC RA
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MOSLSITMS4044, TMS40L444096-WORD BY
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TMS4044, TMS40L444096·WORD BY 1·B
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TMS4044, TMS40L444096·WORD BY l·B
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MILITARYCMOSLSISMJ55172048-WORD BY
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SMJ5517204a·WORD BY a·BIT STATIC
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SMJ55172048·WORD BY 8·BIT STATIC
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SMJ55172048-WDRD BY 8-BIT STATIC RA
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SMJ5517204B·WORD BY B·BIT STATIC
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However, the TMS 4164 provides the
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EXPANSION OF 3242 FOR 256-CYCLE REF
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•9-6
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PAD OPENINGIN OVERCOATPADMETALPADME
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Figure 5 shows how the driver outpu
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cpI UO,leWJOJUI suo'le:>!ldd"f\)W(3
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The falling edge of RAS causes R 1
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~--------::~~:~:~~~:--------~~7,34(
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J-Lead AdvantageTexas Instruments P
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Surface Mount Component Availabilit
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fiSECONDARYVAPOR(VAPOR BLANKET)..Fi
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l>'C'2.ri'Q),..o·:::Jen5'....... o
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l>"C'2..(i"Dl...0":=(I)5"....o...3D
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An external refresh counter has bee
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l>'C'CC:)"Q).-+o·::::sen:ro ... ""
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uo!~ew"oJul suo!~ea!ldd"CD .,.., w7
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DOTCLOCKCLOCK ACLOCK C2 xWCLKRAS (A
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B. If dynamic RAM refresh is enable
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•9-38
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The TMS4416/TMS4500A board is arran
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RAS ~CAS \ I2AI \ I '-2BI '-iiD1Ro2
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9-44
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ALEACXRASMAO-MA7CASFIGURE 1 -ALE LE
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The ALE high to ClK low time is giv
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ClKALEACXRASMAO-MA7CASREFREQROY•
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CDinN~1~12 MHzClKINClKOUTWE/iOclKRD
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UO!leWJOJUI SUOlle:ludd"com~'~,i'74
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coen(J)CLOCKWRITEREADROYALEA14-A5MS
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. Access Grant CyclesThe precharge
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whereta(C)tp(BFR)(-103 + tc2 - tp(B
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•9-62
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tt(REH)TCHLLtAEL-RELRAS rise time (
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. Refresh CyclesOn refresh cycles t
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wherethus,fCLKfCLKtCACfCLK[1/2 (tCA
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R/W approach does a normal read-mod
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II(0~""6 MHzI UO!leWJO,ulSUo!le:l!l
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ClKAlE.ACR\ ,----\,\ ,----R/W\ ,---
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4. Row address setup and hold timeT
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CLKrWRITE -------I.~ ..~---REFRESH-
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The read access time on access gran
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implementations in order to relieve
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"C'2..c:rm...o·j(I)....5'o3...mo·
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RELATIVE MEMORY SIZEARCHIVAL STORAG
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increments till satisfied. This pro
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In the example shown in Figure 5, t
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»'C"E..crQ)r+0':::Jtil:;-....o...3
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•9-94
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184LOGIC SYMBOLS1. INTRODUCTIONEXPl
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LOGIC SYMBOLS4.DIAGRAMATIC SUMMARYI
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lOGIC SYMBOLSWhen RAS goes low, it
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MECHANICAL DATAgeneralElectrical ch
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MECHANICAL DATAceramic packages -ce
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MECHANICAL DATAplastic packages (N
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MECHANICAL DATAceramic chip carrier
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Texas InstrumentsSemiconductor Tech
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TI Sales Offices TI DistributorsALA
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Printed in U.S.A.•TEXASINSTRUMENT
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