1 - Al Kossow's Bitsavers

SMJ441616,384-WORD BY 4-B11 DYNAMIC RAMtiming requirements over recommended supply voltage range and operating case temperature rangetC(PItc(rd)tC(WItc(rdWItw(CH)twlCLItwIRH)twIRL)twlWItttsulCAItsuIRA)tsu(D}tsulrdltsu(WCH)tsu(WRH)th(CLCA)ttl/RAJth(RLCA)th(CLD)th(RLD)th(WLD)thlRHrdlth(CHrd)thlCLWIthIRLW)tRLCHtCHRLtCLRHtCLWLtRLCLtRLWLtWLCLtGHDtrfPARAMETERPage mode cycle timeRead cycle time·Write cycle timeRead-write/read-modify-write cycle timePulse width, CAS high (precharge time)··Pulse width, CAS low TPulse width RAS high (precharge time)Pulse width, RAS low+Write pulse widthTransition times (rise and fall) for RAS and CASColumn address setup timeRow address setup timeData setup timeRead command setup timeWrite command setup time before CAS highWrite command setup time before RAS highColumn address hold time after CAS" lowRow address hold timeColumn address hold time after RAS lowData hold time after CAS lowData hold time after RAS lowData hold time after W lowRead command hold time after RAS highRead command hold time after CAS highWrite command hold time after CAS lowWrite command hold time after RAS lowDelay time, RAS low to CAS highDelay time, CAS high to RAS lowDelay time, CAS low to RAS highDelay time, CAS low to W low(read, modify-write-cycle only)···Delay time, RAS low to CAS low(maximum value specified only to guarantee access time)Delay time, RAS low to W low(read, modify-write-cycle only)···Delay time, W low to CAS low (early write cycle)Delay time, G high before data applied at DORefresh time interval• Note: All cycle times assume tt = 5 ns,•• Page mode only .•• 'Necessary to insure IT has disabled the output buffers prior to applying data to the device.ALT.SMJ4416·12UNITSYMBOL MIN MAXtpc 120 nstRC 230 nstwc 230 ns,·tRWC 320 nstcp 40 nstCAS 70 10,000 nstRP 80 nstRAS 120 10,000 nstwp 30 nstT 3 50 nstASC 0 nstASR 0 nstDS 0 nstRCS 0 nstCWL 50. nstRWL 50 nstCAH 35 nstRAH 15 nstAR 85 nstDH 40 nstDHR 100 nstDH 30 nstRRH 10 ns .tRCH 0 nstWCH 40 nstWCR 100 nstCSH 150 nstCRP 0 nstRSH 80 nstCWD 120 nstRCQ 20 50 nstRWD 170 nstwcs -5 ns30 nstREF 4 mstin a read-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional CAS low time tW(CL)'*In a read-modify-write cycle, tRLWL and.tsu(WRH) must be observed. Depending on the user's transition times, this may require additional RAS low time twIRL)'enQ)U.s:Q)o~oc.C.:::len>...oEQ):!"0t:C'O:!cd:a:u-eC'Ot:>oTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-97