1 - Al Kossow's Bitsavers

TMS4256, TMS4257262,144·8IT DYNAMIC RANDOM·ACCESS MEMORIEStiming requirements over recommended supply voltage range and operating free-air temperature rangeTMS4256-10 TMS4256-12ALT.PARAMETER TMS4257-10 TMS4257-12 UNITSYMBOLMIN MAX MIN MAXtc!PI Page-mode cycle time (read or write cycle) tpc 100 120 nstc(PM) Page-mode cycle time (read-modify-write cycle) tpCM 135 165 nstc(rd) Read cycle time t tRC 200 230 nstC!WI Write cycle time twc 200 230 nstc(rdW) Read-write/read-modify-write cycle time tRWC 235 270 nstw(CH)P Pulse duration, CAS high (page mode) tcp 40 50 nstwlCHI Pulse duration, CAS high (non-page mode) tCPN 40 50 nstw(Cl) Pulse duration, CAS low:t tCAS 50 10,000 60 10,000 nstw(RHI Pulse duration, RAS high (precharge time) tRP 90 100 nstwIRl) Pulse duration, RAS low § tRAS 100 10,000 120 10,000 nstw(WI Write pulse duration twp 35 40 nstt Transition times (rise and fall) for RAS and ~ tT 3 50 3 50 nstsuJCAi Column address setup time tASC 0 0 nstsu(RA) Row address setup time tASR 0 0 nstsu(D) Data setup time tDS 0 0 nstsu(rd) Read command setup time tRCS 0 0 nstsu(WCL)Early write command setup timebefore CAS lowtwcs0 0 nstsulWCHI Write command setup time before CAS high tCWL 30 40 nstsu(WRH) Write command setup time before RAS high tRWL 30 40 nsth(CLCA) Column address hold time after CAS low tCAH 20 20 nsth(RAI Row address hold time tRAH 15 15 nsth(RLCAI Column address hold time after RAS low tAR 70 80 nsthlCLD) Data hold time after CAS low tDH 30 35 nsth(RLD) Data hold time after RAS low tDHR 80 95 nsth(WLD) Data hold time after W low tDH 30 35 nsthiCHrdl Read command hold time after CAS high tRCH 0 0 nsthlRHrdl Read command hold time after RAS high tRRH 10 10 nsth{CLW) Write command hold time after CAS low tWCH 30 35 nsthlRLWI Write command hold time after RAS low tWCR 80 95 nstRLCHR Delay time, RAS low to CAS high 1 tCHR 20 25 nstRLCH Delay time, RAS low to CAS high tCSH 100 120 nstCHRL Delay time, CAS high to RAS low tCRP 0 0 nstCLRH Delay time, CAS low to RAS high tRSH 50 60 nstCLRL Delay time, CAS low to RAS low' tCSR 20 25 nsDelay time, CAS low to W lowtCLWL(read-modify-write cycle only)tCWD 50 60 nsDelay time, RAS low to CAS lowtRLCL (maximum value specified only tRCD 25 50 25 60 nsto guarantee access time)tRLWLDelay time, RAS low to W low(read-modify-write cycle only)tRWD 100 120 nstrf Refresh time interval tREF 4 4 ms.. ..NOTE: Timing measurements are made at the 10% and 90% POints of Input and clock tranSitIOns. In additIOn, VIL max and VIH min must be met at the10% and 90% points.t All cycle times assume tt = 5 ns.:I: In a read-modify-write cycle, tCLWL and tsu(WCHI must be observed. Depending on the user's transition times, this may require additional CAS low time(tw(CLII. This applies to page-mode read-modify-write also.§ In a read-modify-write cycle, tRLWL and tsu(WRHI must be observed. Depending on the user's transition times, this may require additional RAS low time(tw(RLII., CAS before RAS refresh only.......oc.C.::len> ...oE(1)~"Ceca~«a:(.)'Eca·e>C14TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-69