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FPGA Design in VHDL - ALSE

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Speed<strong>in</strong>g up the Validation phase<br />

Very simple Techniques can dramatically improve the<br />

Simulation efficiency, like :<br />

• Automation (GUI → Scripts),<br />

• Test benches should be self-test<strong>in</strong>g & regressionable,<br />

• Don’t eyeball waveforms,<br />

• Use extensively File I/O,<br />

• Use “on-the-fly” comparison,<br />

• Implement <strong>in</strong>teractive tests, ...<br />

© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com

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