FPGA Design in VHDL - ALSE

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System-level test Benches & Verification Tools Design Documentation Data Management Quality Management Know-how Transfer FPGA Design Flow System Analysis & Partitioning Functional Blocks (from Top-Level down) Unitary RTL Coding Unitary Synthesis Unitary Test Bench Functional Verification Unitary Validation System-level Verification System-Level Synthesis Place & Route Post-Layout Simulation Hardware Validation + Final delivery © Bert CUZEAU - ALSE - http://www.alse-fr.com Project Management Méthodology Guide Design reviews “Peer Reviews”... NB : Iterations are not represented in this simplified diagram
Test ! Time to Design ! Morale : Coding time does not need to be accelerated ! (Quality is more important than speed) Debug + Test + Verification is the bottleneck. © Bert CUZEAU - ALSE - http://www.alse-fr.com Analysis RTL Coding Documentation Debugging, Tests & Validation
Page 1 and 2: © ALSE France - Sept 2001 Designin
Page 3: Silicon FPGA, ASIC,... Ground for S
Page 7 and 8: Speeding up the Validation phase Ve
Page 9 and 10: Example : VHDL Code Generator in
Page 11 and 12: Take advantage of the Silicon You m
Page 13 and 14: Conclusion Today more than ever, su
Page 15: A 1 F 0 B 1 0 C 1 0 D 1 0 E 1 0 1 0

FPGA Design in VHDL - ALSE

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