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A 1<br />
F<br />
0<br />
B 1<br />
0<br />
C 1<br />
0<br />
D 1<br />
0<br />
E 1<br />
0<br />
1<br />
0<br />
100 ns<br />
100 ns<br />
100 ns<br />
100 ns<br />
100 ns<br />
Other...<br />
100 ns<br />
X<br />
?<br />
- Appendix B -<br />
<strong>VHDL</strong> Quizz<br />
library IEEE;<br />
use IEEE.std_logic_1164.all;<br />
entity quizz is<br />
end quizz;<br />
architecture test of quizz is<br />
signal nRST : std_logic;<br />
beg<strong>in</strong><br />
process<br />
beg<strong>in</strong><br />
nRST nRST nRST
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