FPGA Design in VHDL - ALSE

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RTL Coding Your HDL coding style must take advantage of : - new tools (HDL synthesis has progressed !) - new components (embedded blocks) • Abandon the discrete FFs & logic style ! • Give up on complex logic Equations ! • No more TTL Macros !!! • + Complex Finite State Machines • + Behavioral RTL (more inference) © Bert CUZEAU - ALSE - http://www.alse-fr.com
Take advantage of the Silicon You may find that some families are better suited to such or such kind of application : • Look at complex macro-functions : pipelined Multipliers, Rams / Roms / Dual Ports, special operators, etc... • Predictability & stability of performances, • Synthesis & Simulation tools, • Efficiency & Ease of use of the Place & Route tools, • etc... © Bert CUZEAU - ALSE - http://www.alse-fr.com
Page 1 and 2: © ALSE France - Sept 2001 Designin
Page 3 and 4: Silicon FPGA, ASIC,... Ground for S
Page 5 and 6: Test ! Time to Design ! Morale : Co
Page 7 and 8: Speeding up the Validation phase Ve
Page 9: Example : VHDL Code Generator in
Page 13 and 14: Conclusion Today more than ever, su
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FPGA Design in VHDL - ALSE

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