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© <strong>ALSE</strong> France - Sept 2001<br />
<strong>Design</strong><strong>in</strong>g Complex <strong>FPGA</strong>s<br />
-do it right, the first time-<br />
Bert CUZEAU<br />
Technical Manager - <strong>ALSE</strong><br />
ASIC / <strong>FPGA</strong> <strong>Design</strong> Expert<br />
Doulos HDL Instructor (Verilog-<strong>VHDL</strong>)<br />
<strong>in</strong>fo@alse-fr.com<br />
http://www.alse-fr.com<br />
: 33.(0)1 45 82 64 01
What is a “Complex” <strong>FPGA</strong> ?<br />
Note : Complex ≠ Dense :<br />
• A 1 Meg gates <strong>FPGA</strong> may be very simple to design...<br />
Some aggravat<strong>in</strong>g factors :<br />
• Asynchronism !<br />
• Poor specs...<br />
• External Environment complex or without model.<br />
• Close to Technological Limits.<br />
• Complex algorithms with<strong>in</strong> few clock cycles.<br />
H<strong>in</strong>t : look at the Test Plan.<br />
© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com
Silicon<br />
<strong>FPGA</strong>, ASIC,...<br />
Ground for Success<br />
Know-How<br />
<strong>Design</strong> Tools<br />
Front / Back-End<br />
Language<br />
<strong>VHDL</strong> '93<br />
© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com<br />
Methodology
System-level test Benches<br />
& Verification Tools<br />
<strong>Design</strong> Documentation<br />
Data Management<br />
Quality Management<br />
Know-how Transfer<br />
<strong>FPGA</strong> <strong>Design</strong> Flow<br />
System Analysis & Partition<strong>in</strong>g<br />
Functional Blocks (from Top-Level down)<br />
Unitary RTL Cod<strong>in</strong>g Unitary Synthesis<br />
Unitary Test Bench<br />
Functional Verification<br />
Unitary Validation<br />
System-level Verification<br />
System-Level Synthesis<br />
Place & Route<br />
Post-Layout Simulation<br />
Hardware Validation + F<strong>in</strong>al delivery<br />
© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com<br />
Project Management<br />
Méthodology<br />
Guide<br />
<strong>Design</strong> reviews<br />
“Peer Reviews”...<br />
NB : Iterations are not<br />
represented <strong>in</strong> this<br />
simplified diagram
Test !<br />
Time to <strong>Design</strong> !<br />
Morale : Cod<strong>in</strong>g time does not need to be accelerated !<br />
(Quality is more important than speed)<br />
Debug + Test + Verification is the bottleneck.<br />
© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com<br />
Analysis<br />
RTL Cod<strong>in</strong>g<br />
Documentation<br />
Debugg<strong>in</strong>g, Tests &<br />
Validation
Simulation is the Key<br />
Advanced Functional Simulation is one<br />
Key to success :<br />
• Shorten, secure and simplify the validation phase.<br />
• Allow for non-regression tests<br />
• Simplify the delivery and acceptance phase.<br />
A clever simulation methodology can have an<br />
<strong>in</strong>credible impact (3 x ga<strong>in</strong>s are common).<br />
=> delays & costs can easily be divided by 2 !<br />
© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com
Speed<strong>in</strong>g up the Validation phase<br />
Very simple Techniques can dramatically improve the<br />
Simulation efficiency, like :<br />
• Automation (GUI → Scripts),<br />
• Test benches should be self-test<strong>in</strong>g & regressionable,<br />
• Don’t eyeball waveforms,<br />
• Use extensively File I/O,<br />
• Use “on-the-fly” comparison,<br />
• Implement <strong>in</strong>teractive tests, ...<br />
© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com
“C”,<br />
MatLab,<br />
etc...<br />
“C”,<br />
MatLab,<br />
etc...<br />
D<strong>in</strong><br />
Dout<br />
Rom<br />
Test Bench Structure Example<br />
U.U.T.<br />
<strong>VHDL</strong> RTL<br />
<strong>VHDL</strong> Test Bench<br />
Console<br />
Results<br />
© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com<br />
Behavioral HDL<br />
models<br />
(µP, memories,<br />
peripherals,<br />
etc…)<br />
?
Example : <strong>VHDL</strong> Code Generator <strong>in</strong> ‘C’<br />
fpr<strong>in</strong>tf fpr<strong>in</strong>tf(fdest<br />
fpr<strong>in</strong>tf fpr<strong>in</strong>tf fdest fdest," fdest ," -- Synthesized Waveform Table\n");<br />
fpr<strong>in</strong>tf fpr<strong>in</strong>tf(fdest<br />
fpr<strong>in</strong>tf fdest fdest," fdest ," -- (c) (c) Bert Bert Cuzeau Cuzeau - <strong>in</strong>fo@ <strong>in</strong>fo@alse<br />
<strong>in</strong>fo@<br />
alse alse-fr alse fr fr.com\n");<br />
.com\n");<br />
fpr<strong>in</strong>tf fpr<strong>in</strong>tf(fdest<br />
fpr<strong>in</strong>tf fdest fdest," fdest ," subtype subtype SLV8 is std_logic_vector std_logic_vector (7 (7 downto 0);\n");<br />
fpr<strong>in</strong>tf fpr<strong>in</strong>tf(fdest<br />
fpr<strong>in</strong>tf fpr<strong>in</strong>tf fdest fdest," fdest ," type Rom64x8 is array (0 to 63) of SLV8;\n");<br />
fpr<strong>in</strong>tf fpr<strong>in</strong>tf(fdest<br />
fpr<strong>in</strong>tf fdest fdest," fdest ," constant S<strong>in</strong>us_ S<strong>in</strong>us_Rom<br />
S<strong>in</strong>us_<br />
Rom : Rom64x8 := (\n ");<br />
for for for (n=0; (n=0; n
RTL Cod<strong>in</strong>g<br />
Your HDL cod<strong>in</strong>g style must take advantage of :<br />
- new tools (HDL synthesis has progressed !)<br />
- new components (embedded blocks)<br />
• Abandon the discrete FFs & logic style !<br />
• Give up on complex logic Equations !<br />
• No more TTL Macros !!!<br />
• + Complex F<strong>in</strong>ite State Mach<strong>in</strong>es<br />
• + Behavioral RTL (more <strong>in</strong>ference)<br />
© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com
Take advantage of the Silicon<br />
You may f<strong>in</strong>d that some families are better suited to such<br />
or such k<strong>in</strong>d of application :<br />
• Look at complex macro-functions : pipel<strong>in</strong>ed Multipliers, Rams /<br />
Roms / Dual Ports, special operators, etc...<br />
• Predictability & stability of performances,<br />
• Synthesis & Simulation tools,<br />
• Efficiency & Ease of use of the Place & Route tools,<br />
• etc...<br />
© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com
Kow-How<br />
• <strong>Design</strong>ers should go through an excellent HDL Tra<strong>in</strong><strong>in</strong>g Course.<br />
• The synthesis & <strong>FPGA</strong> technology know-how should be updated.<br />
• Sound Digital <strong>Design</strong> pr<strong>in</strong>ciples must be understood & enforced !<br />
• A Solid Experience is required (<strong>Design</strong> & Tools)<br />
Note : Excellent <strong>Design</strong>er � Very Simple code...<br />
Beware !<br />
- Not all Books & Tra<strong>in</strong><strong>in</strong>g Courses are good …<br />
- Existent code (Books, In-house, Internet,…) may be of poor<br />
quality or obsolete...<br />
© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com
Conclusion<br />
Today more than ever, success relies upon the <strong>Design</strong>er’s<br />
Know-How and Skills, but a bullet-proof methodology is<br />
mandatory. (“kludges” don’t work any more).<br />
-HDL Languages,<br />
- Synthesis and Simulation Tools and<br />
- Complex Programmable Devices<br />
are not widely available !<br />
Just add the right know-how + a good methodology and attack<br />
the most complex projects !<br />
© Bert CUZEAU - <strong>ALSE</strong> - http://www.alse-fr.com
- Appendix A -<br />
Simple Behavioral send/receive UART !<br />
Transmit (N-8-1) Receive (N-8-1)<br />
TX
A 1<br />
F<br />
0<br />
B 1<br />
0<br />
C 1<br />
0<br />
D 1<br />
0<br />
E 1<br />
0<br />
1<br />
0<br />
100 ns<br />
100 ns<br />
100 ns<br />
100 ns<br />
100 ns<br />
Other...<br />
100 ns<br />
X<br />
?<br />
- Appendix B -<br />
<strong>VHDL</strong> Quizz<br />
library IEEE;<br />
use IEEE.std_logic_1164.all;<br />
entity quizz is<br />
end quizz;<br />
architecture test of quizz is<br />
signal nRST : std_logic;<br />
beg<strong>in</strong><br />
process<br />
beg<strong>in</strong><br />
nRST nRST nRST