2007 ieee international symposium on electromagnetic compatibility
2007 ieee international symposium on electromagnetic compatibility
2007 ieee international symposium on electromagnetic compatibility
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EMC <str<strong>on</strong>g>2007</str<strong>on</strong>g> ADVANCE PROGRAM 23Numerical and Experimental Investigati<strong>on</strong> of Power SupplyNoise Decoupling Strategies <strong>on</strong> Single-Sided PrintedCircuit BoardsBruce Archambeault, IBM; Cyrous Rostamzadeh, Bosch; and SamuelC<strong>on</strong>nor, IBMIn the high-volume and low manufacturing budget of the automotiveworld, printed circuit boards are designed without the use of a dedicatedpower or ground plane. Decoupling capacitors <strong>on</strong> single-sidedprinted circuit boards are c<strong>on</strong>nected between Vcc and return traces.In this paper, we evaluate a number of practical decoupling capacitormounting strategies for these single-sided printed circuit boards usedin the design of automotive c<strong>on</strong>trol modules. The Partial ElementEquivalent Circuit numerical modeling technique is used to validatemeasured data and to explore additi<strong>on</strong>al design opti<strong>on</strong>s.INTEGRATED CIRCUIT EMCThermal Influence <strong>on</strong> 16 Bits Microc<strong>on</strong>troller Emissi<strong>on</strong>S<strong>on</strong>ia Ben Dhia; Etienne Sicard; Alexandre Boyer; and Yoan Mequign<strong>on</strong>,— Institut Nati<strong>on</strong>al des Sciences Appliquées (INSA) of Toulouse; and JeanMarc Dienot, IUT TarbesThis paper deals with the thermal influence <strong>on</strong> integrated circuit performancesin terms of parasitic emissi<strong>on</strong>. Emissi<strong>on</strong> measurementresults c<strong>on</strong>ducted <strong>on</strong> a 16-bit microc<strong>on</strong>troller at extreme temperaturec<strong>on</strong>diti<strong>on</strong>s are provided, showing a difference of 10 dB between -40°C and 125°C. We detail a predictive approach for modeling theemissi<strong>on</strong> level variati<strong>on</strong> with temperature. The simulati<strong>on</strong> takes intoaccount temperature-dependant passive and active device models. Itis shown that the silic<strong>on</strong> substrate, drivers, and <strong>on</strong>-chip capacitanceplay significant roles in the increase in emissi<strong>on</strong> levels when loweringthe operating temperature.Comparis<strong>on</strong> of Radiati<strong>on</strong> from Two Microprocessor TestPackagesXiaopeng D<strong>on</strong>g; Kevin Daniel; and Kevin Slattery, — Intel Corporati<strong>on</strong>Radiati<strong>on</strong> directly from integrated circuits (ICs) packages is c<strong>on</strong>venti<strong>on</strong>allynot c<strong>on</strong>sidered significant since the size of the package iselectrically small and not c<strong>on</strong>sidered as an efficient antenna.However, as the technology evolves and operating frequency increases,the size of the microprocessor package is no l<strong>on</strong>ger electricallysmall. Moreover, in todays and in future mobile platforms such asnotebooks and ultra-mobile devices (UMDs), the high performancewireless communicati<strong>on</strong> system and powerful computing system areintegrated together. It is not necessary to have an efficient antennato couple energy from the noise source to the wireless system anddegrade its performance because of the sensitivity level of the wirelessreceiver. In this paper, the radiati<strong>on</strong> from two microprocessortest packages is compared. The results show that the package designhas significant impact <strong>on</strong> the radiati<strong>on</strong> from the package.Assessment of the DPI Standard for Immunity Simulati<strong>on</strong>of Integrated CircuitsJohan Loeckx; and Georges Gielen, — K. U. LeuvenEnsuring immunity to <strong>electromagnetic</strong> interference (EMI) is a majorchallenge in present designs. Making integrated circuits intrinsicallyless susceptible to interference by adapted circuit design canreduce costs substantially in later stages. It is shown that smallchanges in the circuit topology can increase the immunity of IC’s byseveral orders of magnitude. Being able to predict whether a chipwill pass susceptibility tests before fabricati<strong>on</strong> is essential in order toreduce costs. For this reas<strong>on</strong>, accurate simulati<strong>on</strong> of the standard testmethods is needed. In this paper, a simulati<strong>on</strong> framework is presentedthat allows accurate simulati<strong>on</strong> and predicti<strong>on</strong> of theIEC62132- 4 DPI standard.Efficiency of Embedded On-Chip EMI Protecti<strong>on</strong>s toC<strong>on</strong>tinuous Harm<strong>on</strong>ic and Fast Transient Pulses withRespect to Substrate Injecti<strong>on</strong>Ali Alaeldine, ESEO; Nicolas Lacrampe, LAAS-CNRS; Jean-Luc Levant,ATMEL Nantes; Richard Perdriau, ESEO; Mohamed Ramdani, ESEO;Fabrice Caignet, LAAS-CNRS; Marise Bafleur, LAAS-CNRS; EtienneSicard, LESIA-INSA Toulouse; and M'hamed Drissi, IETR-INSA RennesThis paper presents a comparative study of the efficiency of severalembedded EMI protecti<strong>on</strong>s for integrated circuits (ICs) with respectto direct power injecti<strong>on</strong> (DPI) and very fast transmissi<strong>on</strong>-line pulsing(VF-TLP) into the substrate of the IC. This study involves threefuncti<strong>on</strong>ally identical cores, differing <strong>on</strong>ly by their EMI protecti<strong>on</strong>strategies (RC protecti<strong>on</strong>, isolated substrate, meshed power supplynetwork) which were initially designed for low-emissi<strong>on</strong> designguidelines. Through extensive measurements, a classificati<strong>on</strong>between these strategies is established for both injecti<strong>on</strong> methods,leading to the introducti<strong>on</strong> of design guidelines for the minimizati<strong>on</strong>of c<strong>on</strong>ducted susceptibility to substrate injecti<strong>on</strong>.Investigati<strong>on</strong> <strong>on</strong> ESD Transient Immunity of Integrated CircuitNicolas Lacrampe, LAAS-CNRS; Ali Alaeldine, ESEO; Fabrice Caignet,LAAS-CNRS; Richard Perdriau, ESEO; Marise Bafleur, LAAS-CNRS;Nicolas Nolhier, LAAS-CNRS; and Mohamed Ramadani, ESEOThis paper presents a measurement methodology aimed at predictingthe susceptibility of integrated circuits against electrostatic discharge(ESD) stresses. In our applicati<strong>on</strong>, a Very Fast Transmissi<strong>on</strong> LinePulsing (VF-TLP) test bench is used to inject a disturbance into anIC under operati<strong>on</strong>. For simulati<strong>on</strong> purposes, each part of the testbench is modeled separately, and these models are assembled in orderto obtain a complete model representing both the injecti<strong>on</strong> set-upand the IC itself. The suggested injecti<strong>on</strong> model is validated thanksto correlati<strong>on</strong>s between measurements and simulati<strong>on</strong>s <strong>on</strong> a full custom0.18 µm CMOS IC.Latch-up Like Failure of Power Rail ESD Clamp Circuits inCMOS Integrated Circuits Under System-Level ESD TestMing-Dou Ker; and Cheng-Cheng Yen, — Nati<strong>on</strong>al Chiao-TungUniversity, Hsinchu, TaiwanTwo different <strong>on</strong>-chip power-rail electrostatic discharge (ESD) protecti<strong>on</strong>circuits, <strong>on</strong>e with NMOS and PMOS feedback; and twowith cascaded PMOS feedback, have been designed and fabricatedin a 0.18-μm CMOS technology to investigate their susceptibilityto a system-level ESD test. The main purpose for adopting thefeedback loop into the power-rail ESD clamp circuits is to avoid thefalse triggering during a fast power-up operati<strong>on</strong>. However, duringthe system-level ESD test, where the ICs in a microelectr<strong>on</strong>ics systemhave been powered up, the feedback loop used in the power-railESD clamp circuit provides the lock functi<strong>on</strong> to keep the main ESDdevice in a “latch-<strong>on</strong>” state. The latch-<strong>on</strong> ESD device, which isoften designed with a larger device dimensi<strong>on</strong> to sustain high ESDlevel, c<strong>on</strong>ducts a huge current between the power lines to performa latch-up like failure after the system level ESD test. The susceptibilityof power-rail ESD clamp circuits with the additi<strong>on</strong>al boardlevel noise filter to the system level ESD test is also investigated.To meet high system level ESD specificati<strong>on</strong>s, the chip level ESDprotecti<strong>on</strong> design should be c<strong>on</strong>sidered with the transient noiseduring system level ESD stress. The power-rail ESD clamp circuit©<str<strong>on</strong>g>2007</str<strong>on</strong>g> IEEE www.emc<str<strong>on</strong>g>2007</str<strong>on</strong>g>.org