2007 ieee international symposium on electromagnetic compatibility

More documents

Recommendations

Info

22EMC <strong>2007</strong> ADVANCE PROGRAMmode (DM) current on the signal trace, and cross-talk current on thevictim traces. Consequently, correct predictions of CM current atlower frequencies and cross-talk are keys to the prediction of the totalEMI behavior of the interconnected PCBs, because the DM currenton the signal trace can be predicted by transmission line theory.Power and Ground Bounce Effects on Component PerformanceBased on Printed Circuit Board Edge Termination MethodologiesMark Montrose, Montrose Compliance Services, Inc.; and En-Xiao Liu,Institute of High Performance ComputingPrinted circuit boards (PCBs) are one source of radiated EMI withdigital components being the culprits. To minimize the developmentof common-mode currents within the silicon package of largecurrent consuming circuits, a stable power distribution network(PDN) is required. Any noise (bounce) on either the power or 0 Vreference (ground) plane may cause, simultaneously, switching noise(SSN) or signal integrity (SI) problems, as well as EMI. In addition,if planar bounce exceeds margin levels, components may not function.To ensure a stable PDN is present, decoupling capacitors andburied capacitive structures are mandatory, along with minimizingloop inductance. The uniqueness of this research lies in analyzingplanar bounce that may exceed voltage margin levels from reflectedEM waves that propagate back to components from the physical edgeof the PCB. The edges of a PCB are in reality a high-impedance,non-terminated signal transmission line stub. With each reflection,ringing occurs. The magnitude of this ringing may cause digitalcomponents to have SSN and/or EMI problems. Popular board edgetermination techniques are investigated to determine if a designershould be concerned with reflected wave switching noise on either apower or 0 V reference plane, which cannot be removed by capacitivestructures or decoupling.Analysis of Emissions from a Printed Circuit Board with aConducting Wire Directed in Various DirectionsMasahiro Takashima; Teruo Tobana; Takayuki Sasamori; and Kohshi Abe,— Department of Electronics and Information Systems, Akita PrefecturalUniversityEmissions from a printed circuit board (PCB) with a finite sizebecomes serious when the common mode current is excited on it.The common mode current can occur at connections of conductingwires or at a discontinuity of a line or ground plane on a PCB. Inorder to clarify the relation between a junction of conducting wiresto its emission, the authors analyzed emissions from a PCB with conductingwires directed in the upper direction and the lower directionat the ground edge using the Finite-Difference Time-Domain(FDTD) method. From numerical results, it is shown that in the caseof a conducting wire connected to the upper direction, the radiationpower is the largest. Moreover, for the position of a microstrip line,the radiation power is the largest when the distance between themicrostrip line and the wire is small. Further, the experimentalresults of radiation power show the validity of the numerical results.Radiated Emissions from Proximity Coupled OversizedHeat-SinksDheena Moongilan, AT&T Bell LaboratoriesRadiated emission characteristics of oversized heat sinks that have asurface area substantially larger than the top contact surface of the ICpackage are investigated. The heat sinks are found to radiate at higherlevels when coupled in proximity to the package than the frequenciescontained within the IC package. In this paper oversizedheat sinks are modeled as proximately coupled patch antennas with ashort-circuited Stub. Patch antenna characteristics such as inputimpedance that varies with the feed positions, and the patch resonancefrequencies are applied in the analysis of the radiated emissionscharacteristics of oversized heat sinks. Radiated emission measurmentsfrom a physical proximity coupled patch antenna model and ahighly integrated PCB with oversized heat sink are presented and theresults discussed.Modeling and Measurement of Mutual Coupling Resultingfrom Arbitrary 3-D Structures within Printed Circuit BoardDesignsLeigh Cornock; and Ian Dilworth, — University of EssexWe report measurements and modeling of mutual coupling resultingfrom closely spaced copper plated through holes on printed circuitboards (PCB), known as vias. When the magnetic flux generated bya primary system couples with the inductance of a secondary system,a ‘reflected impedance’ is induced in series with the primary inductance.Our investigation includes practical measurements and electromagnetic(EM) modeling using the Transmission Line Matrix(TLM) code in order to establish the change in coupling and ‘reflectedimpedance’ as a function of distance between quasi resonant structures.With significant numbers of coupled vias, possible couplingpermutations are large. We report models for 2, 3, and 4 via coupling,the results from which are extendable to arbitrary 3D structures.PRINTED CIRCUIT BOARD EMC IIPPW Noise Mitigation in Multilayer PCBs by Means ofVirtual Island and/or Array of Shorting ViasAntonio Ciccomancini, CST of AmericaThis paper describes the parallel-plate waveguide (PPW) noise mitigationby means of shorting vias and/or virtual islands. The proposedmethod is already know in literature, nevertheless importantconsiderations are addressed here: 1) the same noise mitigation levelcan be achieved by using only shorting vias or virtual island in combinationwith shorting vias, 2) the noise mitigation is strictly relatedto the number of shorting vias, the position and the distance fromthe signal via, and 3) the PPW noise suppression is effective only ifan array of shorting vias is used. The mitigation level is investigatedboth in the time domain and frequency domain. Different configurationsare studied and the impact of the power plane withetched slots due to virtual islands on the signal quality is also analyzed(TDR and insertion loss).Suppression Effect of Emissions from a Printed CircuitBoard Using a Conducting PlateTeruo Tobana; Takayuki Sasamori; and Kohshi Abe, — Akita PrefecturalUniversityFor emissions caused by the common-mode current on a printedcircuit board (PCB), a suppression method based on the image theoryof placing a conducting plate under the PCB is presented. Inorder to evaluate the suppression effect by this method, the radiationpower from the PCB is calculated using the FDTD method.The numerical results show that by placing the conducting platenear the ground side of the PCB, the emissions from the commonmodecurrent are effectively suppressed. Especially, using the conductingplate with bent sides, it is possible to suppress the emissionsby the small conducting plate. Moreover, the method ofbending the edges of the PCB is presented and it is shown that alarge suppression effect is obtained using this method. Further, theexperimental results of a maximum electric field intensity show thevalidity of the numerical results.©<strong>2007</strong> IEEE www.emc<strong>2007</strong>.org
EMC <strong>2007</strong> ADVANCE PROGRAM 23Numerical and Experimental Investigation of Power SupplyNoise Decoupling Strategies on Single-Sided PrintedCircuit BoardsBruce Archambeault, IBM; Cyrous Rostamzadeh, Bosch; and SamuelConnor, IBMIn the high-volume and low manufacturing budget of the automotiveworld, printed circuit boards are designed without the use of a dedicatedpower or ground plane. Decoupling capacitors on single-sidedprinted circuit boards are connected between Vcc and return traces.In this paper, we evaluate a number of practical decoupling capacitormounting strategies for these single-sided printed circuit boards usedin the design of automotive control modules. The Partial ElementEquivalent Circuit numerical modeling technique is used to validatemeasured data and to explore additional design options.INTEGRATED CIRCUIT EMCThermal Influence on 16 Bits Microcontroller EmissionSonia Ben Dhia; Etienne Sicard; Alexandre Boyer; and Yoan Mequignon,— Institut National des Sciences Appliquées (INSA) of Toulouse; and JeanMarc Dienot, IUT TarbesThis paper deals with the thermal influence on integrated circuit performancesin terms of parasitic emission. Emission measurementresults conducted on a 16-bit microcontroller at extreme temperatureconditions are provided, showing a difference of 10 dB between -40°C and 125°C. We detail a predictive approach for modeling theemission level variation with temperature. The simulation takes intoaccount temperature-dependant passive and active device models. Itis shown that the silicon substrate, drivers, and on-chip capacitanceplay significant roles in the increase in emission levels when loweringthe operating temperature.Comparison of Radiation from Two Microprocessor TestPackagesXiaopeng Dong; Kevin Daniel; and Kevin Slattery, — Intel CorporationRadiation directly from integrated circuits (ICs) packages is conventionallynot considered significant since the size of the package iselectrically small and not considered as an efficient antenna.However, as the technology evolves and operating frequency increases,the size of the microprocessor package is no longer electricallysmall. Moreover, in todays and in future mobile platforms such asnotebooks and ultra-mobile devices (UMDs), the high performancewireless communication system and powerful computing system areintegrated together. It is not necessary to have an efficient antennato couple energy from the noise source to the wireless system anddegrade its performance because of the sensitivity level of the wirelessreceiver. In this paper, the radiation from two microprocessortest packages is compared. The results show that the package designhas significant impact on the radiation from the package.Assessment of the DPI Standard for Immunity Simulationof Integrated CircuitsJohan Loeckx; and Georges Gielen, — K. U. LeuvenEnsuring immunity to electromagnetic interference (EMI) is a majorchallenge in present designs. Making integrated circuits intrinsicallyless susceptible to interference by adapted circuit design canreduce costs substantially in later stages. It is shown that smallchanges in the circuit topology can increase the immunity of IC’s byseveral orders of magnitude. Being able to predict whether a chipwill pass susceptibility tests before fabrication is essential in order toreduce costs. For this reason, accurate simulation of the standard testmethods is needed. In this paper, a simulation framework is presentedthat allows accurate simulation and prediction of theIEC62132- 4 DPI standard.Efficiency of Embedded On-Chip EMI Protections toContinuous Harmonic and Fast Transient Pulses withRespect to Substrate InjectionAli Alaeldine, ESEO; Nicolas Lacrampe, LAAS-CNRS; Jean-Luc Levant,ATMEL Nantes; Richard Perdriau, ESEO; Mohamed Ramdani, ESEO;Fabrice Caignet, LAAS-CNRS; Marise Bafleur, LAAS-CNRS; EtienneSicard, LESIA-INSA Toulouse; and M'hamed Drissi, IETR-INSA RennesThis paper presents a comparative study of the efficiency of severalembedded EMI protections for integrated circuits (ICs) with respectto direct power injection (DPI) and very fast transmission-line pulsing(VF-TLP) into the substrate of the IC. This study involves threefunctionally identical cores, differing only by their EMI protectionstrategies (RC protection, isolated substrate, meshed power supplynetwork) which were initially designed for low-emission designguidelines. Through extensive measurements, a classificationbetween these strategies is established for both injection methods,leading to the introduction of design guidelines for the minimizationof conducted susceptibility to substrate injection.Investigation on ESD Transient Immunity of Integrated CircuitNicolas Lacrampe, LAAS-CNRS; Ali Alaeldine, ESEO; Fabrice Caignet,LAAS-CNRS; Richard Perdriau, ESEO; Marise Bafleur, LAAS-CNRS;Nicolas Nolhier, LAAS-CNRS; and Mohamed Ramadani, ESEOThis paper presents a measurement methodology aimed at predictingthe susceptibility of integrated circuits against electrostatic discharge(ESD) stresses. In our application, a Very Fast Transmission LinePulsing (VF-TLP) test bench is used to inject a disturbance into anIC under operation. For simulation purposes, each part of the testbench is modeled separately, and these models are assembled in orderto obtain a complete model representing both the injection set-upand the IC itself. The suggested injection model is validated thanksto correlations between measurements and simulations on a full custom0.18 µm CMOS IC.Latch-up Like Failure of Power Rail ESD Clamp Circuits inCMOS Integrated Circuits Under System-Level ESD TestMing-Dou Ker; and Cheng-Cheng Yen, — National Chiao-TungUniversity, Hsinchu, TaiwanTwo different on-chip power-rail electrostatic discharge (ESD) protectioncircuits, one with NMOS and PMOS feedback; and twowith cascaded PMOS feedback, have been designed and fabricatedin a 0.18-μm CMOS technology to investigate their susceptibilityto a system-level ESD test. The main purpose for adopting thefeedback loop into the power-rail ESD clamp circuits is to avoid thefalse triggering during a fast power-up operation. However, duringthe system-level ESD test, where the ICs in a microelectronics systemhave been powered up, the feedback loop used in the power-railESD clamp circuit provides the lock function to keep the main ESDdevice in a “latch-on” state. The latch-on ESD device, which isoften designed with a larger device dimension to sustain high ESDlevel, conducts a huge current between the power lines to performa latch-up like failure after the system level ESD test. The susceptibilityof power-rail ESD clamp circuits with the additional boardlevel noise filter to the system level ESD test is also investigated.To meet high system level ESD specifications, the chip level ESDprotection design should be considered with the transient noiseduring system level ESD stress. The power-rail ESD clamp circuit©<strong>2007</strong> IEEE www.emc<strong>2007</strong>.org
Page 3 and 4: WELCOME FROM THE CHAIRJanet O’Nei
Page 5 and 6: Why Meet The StandardsWhen You Can
Page 7 and 8: Come see us at theIEEE EMC Symposiu
Page 9 and 10: EMC 2007 ADVANCE P
Page 14 and 15: 14EMC 2007 ADVANCE
Page 21: EMC 2007 ADVANCE P
Page 45 and 46: WORKSHOPS - 8 and 9 July 20
Page 53 and 54: 10'IEEE EMC SYMPOSIUMJULY 10-12, <s
Page 57 and 58: SOCIAL ACTIVITIESEMC 2007</

2007 ieee international symposium on electromagnetic compatibility

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?