14EMC <str<strong>on</strong>g>2007</str<strong>on</strong>g> ADVANCE PROGRAMcoupling occurs both horiz<strong>on</strong>tally as well as vertically across layers.Thus, to catch SI and PI problems at an early stage of design requiresfast signal and power co-simulati<strong>on</strong> methodologies. In this paper, weoutline the multi-layer finite-difference method and how the accuracyof the technique can be enhanced with models for fringe and gapeffects. We then briefly describe a method for integrating the signaldistributi<strong>on</strong> network with the power distributi<strong>on</strong> network to enableco-simulati<strong>on</strong>. The method is then applied to a mixed signal boardc<strong>on</strong>taining split planes, and numerical results are compared to fullwavesimulati<strong>on</strong>s.N<strong>on</strong>linear Identificati<strong>on</strong> of Complex Systems Using RadialBasis Functi<strong>on</strong> Networks and Model Order Reducti<strong>on</strong>Werner John; Christopher Wiegand; Ljubica Radic-Weissenfeld; ChristianHedayat; and Ulrich Hilleringmann, — Fraunhofer Institute of Reliabilityand Microintegrati<strong>on</strong>, Advanced System Engineering (FhG IZM ASE),Paderborn, GermanyAs wiring density increases with integrati<strong>on</strong> and miniaturizati<strong>on</strong> ofpackages (SIP) and PCB, the ability to simulate precisely the signalintegrity (SI) behaviour of complex systems becomes decisive, whilethe simulati<strong>on</strong> time increases dramatically. Therefore it is essentialthat the design of such complex systems is supported by accuratesimulati<strong>on</strong> models. This paper proposes a methodology for the identificati<strong>on</strong>and the fast simulati<strong>on</strong> of n<strong>on</strong>-linear complex HDI/HDPsystems and integrated circuits by means of radial basis functi<strong>on</strong>(RBF) nets. For this purpose a specific modelling technique is presentedwith a complete flow that leads to the development of a blackbox model (BBM). This approach is then combined with the modelorder reduced (MOR) attempt and allows accelerated simulati<strong>on</strong> of awhole transmissi<strong>on</strong> line-buffer set.Transmissi<strong>on</strong> Line Model for the Gapped Power Bus StructureJoe Trinkle; and Ant<strong>on</strong>io Cant<strong>on</strong>i, — The Universtity of Western AustraliaA transmissi<strong>on</strong> line model is developed for the computati<strong>on</strong> of thetransfer impedance between gapped supply z<strong>on</strong>es. The model isshown to be accurate to high frequencies by validati<strong>on</strong> with full wavesimulati<strong>on</strong>.Fast Macromodel-based Signal Integrity Assessment for RFand Mixed-Signal ModulesPietro Brenner, Infine<strong>on</strong> Technologies AG, Germany; Flavio Canavero,Politecnico di Torino; and Stefano Grivet-Talocia, Politecnico di TorinoThis paper presents a macromodel-based approach for fast signalintegrity assessment for highly integrated Radio Frequency (RF) andMixed-Signal System <strong>on</strong> Chip (SoC) applicati<strong>on</strong>s. In particular, weintroduce a complexity reducti<strong>on</strong> process that enables the signalintegrity verificati<strong>on</strong> via analog circuit simulati<strong>on</strong>s, and we apply themethodology to complex radio transceiver chips in order to characterizethe influence of parasitic elements <strong>on</strong> the signal processing performanceof the system. Some preliminary tests show that the proposedmethodology leads to significant simulati<strong>on</strong> speed-up factorswith respect to standard approaches for the specific applicati<strong>on</strong> herewithc<strong>on</strong>sidered.Determinati<strong>on</strong> of Propagati<strong>on</strong> of Fast Induced TransientImpulses <strong>on</strong> PCB-LevelWerner John; and Mohamed Taki, — Fraunhofer Institute of Reliabilityand Microintegrati<strong>on</strong>, Advanced System Engineering (FhG IZM ASE),Paderborn, GermanyIn this c<strong>on</strong>tributi<strong>on</strong>, an extended approach to determine the flow ofinduced transient noise injected into a system of interc<strong>on</strong>nects will bepresented. It is now possible to create subcircuits for detailed analysisand use more than <strong>on</strong>e noise source. Dominant and critical signaltraces that transfer significant noise, form multiple noise sources thatcouple with digital device input ports and are determined in the frequencydomain using advanced graph searching algorithms. Thetime domain simulati<strong>on</strong> of the whole signal paths, including devicedrivers and receivers, is performed using a hybrid analysis in HSpiceenvir<strong>on</strong>ment. The approach is applied to an interc<strong>on</strong>nect systemdriven by two sensitive inverter gates. The scattering parameters andthe waveform of the propagating impulses c<strong>on</strong>sidering dominant signalpaths show good agreement with the total system resp<strong>on</strong>se.SPECIAL SESSION: POWER INTEGRITY / SIGNAL INTEGRITYFOR NEXT GENERATION SYSTEMSBroadband Noise Suppressi<strong>on</strong> Using a Hybrid Phot<strong>on</strong>icCrystal Power/Ground Plane SubstrateTz<strong>on</strong>g-Lin Wu, Nati<strong>on</strong>al Taiwan University; Yi-Che Chen, Nati<strong>on</strong>alTaiwan University; Ting-Kuang Wang, Nati<strong>on</strong>al Taiwan University; AlexLu, N/A; and Lexus Lan, N/AA novel hybrid phot<strong>on</strong>ic crystal power/ground layer (H-PCPL) c<strong>on</strong>ceptis proposed with broadband power noise isolati<strong>on</strong> (or suppressi<strong>on</strong>)performance. Two different hybrid approaches are investigated;<strong>on</strong>e is fixed radius but varied pitch for the high-DK disc, and theother <strong>on</strong>e is varied radius and pitch for the disc. It is found the firstapproach can enhance the bandwidth of the noise rejecti<strong>on</strong> but cannot obtain a c<strong>on</strong>tinuous and wide stopband because there is anabsolute passband between two gaps. However, the sec<strong>on</strong>d approachcan obtain a c<strong>on</strong>tinuous and wide stopband by mixing two radius ofthe disc. Gap map of the phot<strong>on</strong>ic crystal lattice is employed to synthesizethe stopband profile in both approaches. As an example, awide stopband ranging from 2.8 GHz to 7.9 GHz can be achievedbased <strong>on</strong> two kinds of radius, 2 mm and 1.45 mm, under the samedisc pitch 10 mm, the effective series inductance of the capacitors.Load Current Funneling Examinati<strong>on</strong> for Power Distributi<strong>on</strong>in High Performance Multi-core Silic<strong>on</strong> DevicesJoseph T. DiBene, II, Intel Corporati<strong>on</strong>Powering silic<strong>on</strong> devices today are challenging due to the increasing c<strong>on</strong>centrati<strong>on</strong>of current into the load at the silic<strong>on</strong>. As multi-core processingbecomes more available, larger numbers of computati<strong>on</strong>al units areplaced <strong>on</strong> a single piece of silic<strong>on</strong> allowing more processing and higherbandwidth in our computer systems. However, as the devices becomesmaller, the current density also increases which raises some fundamentalquesti<strong>on</strong>s <strong>on</strong> the impacts at the interc<strong>on</strong>nect level and the performance ofthe power distributi<strong>on</strong> network in general. This paper discusses the issueof current funneling into high density devices particularly around theadvent of multi-core processing and discusses some of the issues andeffects <strong>on</strong>e may see as the technology moves forward into the future.Power Delivery for High Performance Processor Packages,Part IDavid Hockans<strong>on</strong>, Sun Microsystems, Inc.; and Joseph T.Dibene II, IntelCorporati<strong>on</strong>The c<strong>on</strong>tinued reducti<strong>on</strong> in processor core voltage, increases in currentrequired, and chip density and size place more pressure <strong>on</strong> effectivelyc<strong>on</strong>trolling the impedance of a CPU power distributi<strong>on</strong> system.Voltage fluctuati<strong>on</strong>s across the die limit functi<strong>on</strong>ality andspeed. The core-power path from the die to the voltage regulator isdiscussed herein. The path is separated into segments, and a <strong>on</strong>edimensi<strong>on</strong>alcircuit model is created to aid in the discussi<strong>on</strong>.©<str<strong>on</strong>g>2007</str<strong>on</strong>g> IEEE www.emc<str<strong>on</strong>g>2007</str<strong>on</strong>g>.org
EMC <str<strong>on</strong>g>2007</str<strong>on</strong>g> ADVANCE PROGRAM15Multi-Gigabit I/O Link Circuit Design Challenges andTechniquesJoe Wu, Intel Corporati<strong>on</strong>; and Joseph T. DiBene, II, Intel Corporati<strong>on</strong>This paper describes the major challenges in designing multi-Gigabit I/O link CMOS circuits. Techniques to overcome thechallenges are presented, including transceiver design, discrete andc<strong>on</strong>tinuous time equalizati<strong>on</strong>, terminati<strong>on</strong> c<strong>on</strong>trol, and clockingcircuits.Get Ready For TheNext WaveIn EMI ReceiversIntegrated Circuit Architecture Impacts <strong>on</strong> Applicati<strong>on</strong>Signal IntegrityRoss Carlt<strong>on</strong>, FreescaleIncreasing operati<strong>on</strong>al and data frequencies of integrated circuitsis making system design more costly and challenging as designerscope with signal integrity impacts. An understanding of thearchitecture and design of integrated circuit input/output circuitsand packaging technology can prevent undesired performancedegradati<strong>on</strong> and maximize reliability. This presentati<strong>on</strong> will discussa few of the aspects of IC and package design that impact signalintegrity.Early Time Charge Replenishment of the Power DeliveryNetwork in Multi-Layer PCBsGiuseppe Selli, University of Missouri-Rolla; Matteo Cocchini, University ofMissouri-Rolla; James Knighten, NCR Corporati<strong>on</strong>; Bruce Archambeault,IBM Corporati<strong>on</strong>; Jun Fan, NCR Corporati<strong>on</strong>; Samuel C<strong>on</strong>nor, IBMCorporati<strong>on</strong>; Ant<strong>on</strong>io Orlandi, University of L'Aquila; and JamesDrewniak, University of Missouri-RollaThe investigati<strong>on</strong> of decoupling issues has been extensively treated inthe literature in both the frequency and the time domain. The twodomains describe from different perspectives the same physical phenomen<strong>on</strong>,being related by a Fourier transform. In this paper, wellknown decoupling issues usually addressed in the frequency domainare discussed in the time domain. Moreover, some modeling issuesrelated to the cavity model approach are discussed and, in particular,the circuit extracti<strong>on</strong> feature associated with this methodology is utilizedthroughout the paper to carry out the time domain simulati<strong>on</strong>swithin a SPICE based tool. The depleti<strong>on</strong> of charges stored betweenthe power bus is investigated in the time domain as a functi<strong>on</strong> of theplane thickness, SMT decoupling closeness, and interc<strong>on</strong>nect inductancevalues.SPECIAL SESSION: ELECTRONIC PACKAGING EMC ANDSIGNAL INTEGRITYNoise Isolati<strong>on</strong> in LTCC-based X/Ku-band Transceiver SiPUsing a Double-Stacked Electromagnetic Bandgap StructureJ<strong>on</strong>gbae Park, Korea Advanced Institute of Science and Technology (KAIST);Junchul Kim, N/A; Albert Chee W. Lu, N/A; Yuje<strong>on</strong>g Shim, KAIST; andJoungho Kim, KAISTWe experimentally investigate the isolati<strong>on</strong> effect of the noisecoupling in an X/Ku-band transceiver SiP fabricated <strong>on</strong> a lowtemperatureco-fired-ceramic (LTCC) multilayer substrate, usinga double-stacked <strong>electromagnetic</strong> bandgap (DS-EBG) structure.The fabricated transceiver SiP is composed of a Ku-band transmitterand X/Ku-band receiver. To prevent the simultaneousswitching noise coupling from digital circuits, a DS-EBG structurewas designed and implemented to the transceiver SiP. Theeffect of the DS-EBG, which gives a 30 dB stopband over X/Kubandranges, was dem<strong>on</strong>strated through frequency and timedomain measurements.The CER2018 Compliant Emissi<strong>on</strong>s Receiveris here. And in many ways it’s unlike any receiver thatcame before it.This complete EMI test soluti<strong>on</strong> offers c<strong>on</strong>tinuouscoverage from 20 Hz to 18 GHz with expandability to110 GHz. And to ensure the highest accuracy, itself-calibrates <strong>on</strong>-demand at every frequency scan.It includes a built-in computer that operates underWindows XP. Software is also included free al<strong>on</strong>g with a19” flat screen m<strong>on</strong>itor, keyboard and mouse.Programmed-in test formats include CISPR 16-1-1,MIL-STD 461/462, ANSI C63 and FCC. Allfuncti<strong>on</strong>s are menu-driven. There is no need to fiddlewith switches, butt<strong>on</strong>s or sliders.Like all AR products, the CER2018 is backed by thebest and most comprehensive warranty in the business.AR is here to help you – today, tomorrow and always.To learn more, visit us at www.ar-worldwide.comor for technical support: call 800-964-1424 (within U.S.)or 818-700-0330.receiver systemsOther ar divisi<strong>on</strong>s: rf/microwave instrumentati<strong>on</strong> • modular rf • ar europeCopyright© <str<strong>on</strong>g>2007</str<strong>on</strong>g> AR. The orange stripe <strong>on</strong> AR products is Reg. U.S. Pat. & TM. Off.©<str<strong>on</strong>g>2007</str<strong>on</strong>g> IEEE www.emc<str<strong>on</strong>g>2007</str<strong>on</strong>g>.org