ARM DS-5 Using the Debug Hardware Configuration Utilities

Creating debug hardware target configurations5.33 CoreSight device names and classesThe following table shows the name and class of all CoreSight devices that are supported by thedebug hardware:Table 5-2 CoreSight device names and classesDevice name Description Device classARMCS-DPARM CoreSight debug port (supports both JTAG-DP andSW-DP)Debug portCSETB CoreSight Embedded Trace Buffer (ETB) Trace sinkCSETM CoreSight Embedded Trace Macrocell (ETM) Trace sourceCSETM11CoreSight Embedded Trace Macrocell designed for ARM11(ETM11)Trace sourceCSTFUNNEL CoreSight Trace Funnel LinkCSTPIU CoreSight Trace Port Interface Unit Trace sinkCSHTM32 CoreSight AHB Trace Macrocell (HTM32) Trace sourceCSHTM64 CoreSight AHB Trace Macrocell (HTM64) Trace sourceCSITM CoreSight Instrumentation Trace Macrocell (ITM) Trace sourceCSPTM CoreSight Program Trace Macrocell (ITM) Trace sourceCSSWO CoreSight Serial Wire Output (SWO) Trace sinkARM1136JFS-JTAG-AP ARM1136JF-S processor connected using JTAG-AP CoreARM1156T2FS-JTAG-AP ARM1156T2FS processor connected using JTAG-AP CoreARM1176JZF-JTAG-AP ARM1156T2FS processor connected using JTAG-AP CoreCortex-M0 Cortex-M0 processor CoreCortex-M1 Cortex-M1 processor CoreCortex-M3 Cortex-M3 processor CoreCortex-R4 Cortex-R4 processor CoreCortex-A5 Cortex-A5 processor CoreCortex-A8 Cortex-A8 processor CoreCortex-A9 Cortex-A9 processor CoreThe device names are the names used in debug hardware configurations and trace associationfiles.5.33.1 See alsoConcepts• Defining CoreSight trace associations on page 6-7• CoreSight topology and associations for the CoreSight DK11 on page 6-15• CoreSight topology and associations for the Cortex-R4 FPGA on page 6-17• CoreSight topology and associations for the Cortex-M3 FPGA on page 6-19• CoreSight topology and associations for multiple trace sources on page 6-21.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 5-52ID021112Non-Confidential