ARM DS-5 Using the Debug Hardware Configuration Utilities

Creating debug hardware target configurations5.20 Debug hardware Advanced configuration reset options5.20.1 See alsoThe following Advanced configuration settings are available when configuring reset options indebug hardware:Allow ICE to latch System Reset (AllowICELatchSysRst)When enabled, this option enables the debug hardware unit to extend the time thetarget controller holds the target in reset. This enables the debug hardware unit toapply breakpoint settings before the processor starts execution. This is useful fordebugging a target from reset, and allows the unit to stop the processor on the firstinstruction fetch after reset has been released by the unit.When this option is disabled, the breakpoint settings might only take effect afterthe processor has already started execution, preventing debugging of theapplication reset handler.The default setting is True.Allow ICE to perform TAP Reset (AllowICETAPReset)A Test Access Port (TAP) reset on early processors, such as the ARM7TDMI, alsoreset the debug registers associated with the JTAG device.Later processor, such as the ARM1176, are not affected by a TAP reset. The mainpurpose of a TAP reset is to reset the JTAG state machine in the TAP controllerreceiving commands from the debug hardware unit.The default setting is True.Concepts• Configuring SecurCore behavior if the processor clock stops when stepping instructionson page 5-38• Configuring TrustZone enabled processor behavior when debug privileges are reduced onpage 5-39.Reference• Debug hardware Advanced configuration settings on page 5-33.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 5-37ID021112Non-Confidential