ARM DS-5 Using the Debug Hardware Configuration Utilities

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Creating debug hardware target configurations5.19 Debug hardware Trace configuration settings5.19.1 See alsoThe Trace configuration settings enable you to configure delays on the trace lines:Delay Trace Clock, Delay Trace Signal NDelay line N by a specified amount of time, expressed in intervals of 75picosecond. Default delays are configured into the unit, and you are able to delayeach signal by a specified amount relative to these defaults, to allow for variationsin target hardware.Invert Trace ClockInvert the clock so that data is sampled on the falling edge, rather than on therising edge, of the clock.Tasks• Configuring trace lines (DSTREAM and RVT2 only) on page 7-4• Configuring your debugger for trace capture on page 7-6.Concepts• About using trace hardware on page 7-2.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 5-36ID021112Non-Confidential
Creating debug hardware target configurations5.20 Debug hardware Advanced configuration reset options5.20.1 See alsoThe following Advanced configuration settings are available when configuring reset options indebug hardware:Allow ICE to latch System Reset (AllowICELatchSysRst)When enabled, this option enables the debug hardware unit to extend the time thetarget controller holds the target in reset. This enables the debug hardware unit toapply breakpoint settings before the processor starts execution. This is useful fordebugging a target from reset, and allows the unit to stop the processor on the firstinstruction fetch after reset has been released by the unit.When this option is disabled, the breakpoint settings might only take effect afterthe processor has already started execution, preventing debugging of theapplication reset handler.The default setting is True.Allow ICE to perform TAP Reset (AllowICETAPReset)A Test Access Port (TAP) reset on early processors, such as the ARM7TDMI, alsoreset the debug registers associated with the JTAG device.Later processor, such as the ARM1176, are not affected by a TAP reset. The mainpurpose of a TAP reset is to reset the JTAG state machine in the TAP controllerreceiving commands from the debug hardware unit.The default setting is True.Concepts• Configuring SecurCore behavior if the processor clock stops when stepping instructionson page 5-38• Configuring TrustZone enabled processor behavior when debug privileges are reduced onpage 5-39.Reference• Debug hardware Advanced configuration settings on page 5-33.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 5-37ID021112Non-Confidential
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®ARMDS-5Version 5.9Using the Debug
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Conformance NoticesThis section con
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Contents4.6 Restarting the debug ha
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Contents10.6 Auto Configure button
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Conventions and feedback• the ser
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Getting started with the debug hard
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Chapter 3Configuring network settin
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Configuring network settings for yo
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Chapter 8Debugging with your debug
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Debugging with your debug hardware
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Chapter 9Configuring debug hardware
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Configuring debug hardware for GDB9
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Configuring debug hardware for GDBO
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Configuring debug hardware for GDBR
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Configuring debug hardware for GDB
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Chapter 10Troubleshooting your debu
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Troubleshooting your debug hardware
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ARM DS-5 Using the Debug Hardware Configuration Utilities

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