ARM DS-5 Using the Debug Hardware Configuration Utilities

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Creating debug hardware target configurationsPerform SYS reset on first connectResets the target hardware by asserting the nSRST signal when connecting to thefirst device in a debug session.Reset TypeOne of the following:nSRSTResets the hardware by holding the hardware nSRSTsystem reset signal LOW. This is the default.nTRSTResets the target TAP by holding the nTRST TAP resetsignal LOW.nSRST+nTRST Resets the hardware and the target TAP by holding both thehardware nSRST system reset signal and the nTRST TAPreset signal LOW.FakeResets the system by entering supervisor mode, and settingthe program counter to the address of the reset vector(known as a soft reset).Ctrl_Reg The Control register. This reset, in instances whereprocessors have a reset register, enables you to reset theprocessor without using the external reset lines. If you setthe reset type to Ctrl_Reg, then this control register is used.SWO Mode Set to Manchester or UART, depending on the target mode.If the SWO Mode is set to UART, the debug hardware unit is able to detect theSWO UART Baud rate.This setting has no effect in Manchester mode.SWO UART Baud rateFor the frequency of the incoming data. If you set this to 0, the system attemptsto autodetect the baud rate.NoteUART mode in the SWO context also means Non Return to Zero (NRZ) mode.TAP Reset via State TransitionsIf you want the JTAG logic in the target hardware to be reset by forcing transitionswithin its state machine. This is done in addition to holding the nTRST TAP resetsignal LOW. Select this option if nTRST is not connected, or if the targethardware requires that you force a reset of the JTAG logic whenever resetting.Target nSRST + nTRST linkedIf the target hardware has its nSRST and nTRST JTAG signals linked.Use SWJ SwitchingIf this is set, it causes the SWJ switching sequence to be sent before connectingto the target device. On devices that support SWJ switching, this causes the DAPto switch its interface to the selected protocol.NoteIf a target supports both JTAG and SWD, you must enable this setting before youautoconfigure that target.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 5-34ID021112Non-Confidential
Creating debug hardware target configurationsUse deprecated SWJ SequenceIf this is set, it causes your debug hardware unit to use an alternative SWJswitching sequence, used on some older SWD-compatible targets. This option isnormally clear, unless the processor requires the deprecated sequence.NoteFor RVI, the LVDS Debug Interface mode, Use SWJ Switching, and Usedeprecated SWJ Sequence controls are not present in the control pane if you arenot using a Low Voltage Differential Signaling (LVDS) probe.User OutputnUsed to set the state of the USER IO pins on the rear of the RVI unit, or on thefront of the DSTREAM unit.5.18.1 See alsoTasks• Configuring the debug hardware Advanced settings on page 5-47.• Debugging with a reset register on page 8-20.ReferenceARM DSTREAM System and Interface Design Reference:• DSTREAM reset signals on page 2-7.ARM RVI and RVT System and Interface Design Reference:• RVI reset signals on page 2-7.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 5-35ID021112Non-Confidential
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®ARMDS-5Version 5.9Using the Debug
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Conformance NoticesThis section con
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Contents4.6 Restarting the debug ha
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Contents10.6 Auto Configure button
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Conventions and feedback• the ser
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Getting started with the debug hard
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Chapter 3Configuring network settin
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Configuring network settings for yo
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Configuring network settings for yo
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Using TraceConcepts• About using
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Chapter 8Debugging with your debug
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Debugging with your debug hardware
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Chapter 9Configuring debug hardware
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Configuring debug hardware for GDB9
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Configuring debug hardware for GDBO
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Configuring debug hardware for GDBR
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Configuring debug hardware for GDB
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Chapter 10Troubleshooting your debu
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Troubleshooting your debug hardware
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ARM DS-5 Using the Debug Hardware Configuration Utilities

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