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ARM DS-5 Using the Debug Hardware Configuration Utilities

ARM DS-5 Using the Debug Hardware Configuration Utilities

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Creating debug hardware target configurationsPerform SYS reset on first connectResets <strong>the</strong> target hardware by asserting <strong>the</strong> nSRST signal when connecting to <strong>the</strong>first device in a debug session.Reset TypeOne of <strong>the</strong> following:nSRSTResets <strong>the</strong> hardware by holding <strong>the</strong> hardware nSRSTsystem reset signal LOW. This is <strong>the</strong> default.nTRSTResets <strong>the</strong> target TAP by holding <strong>the</strong> nTRST TAP resetsignal LOW.nSRST+nTRST Resets <strong>the</strong> hardware and <strong>the</strong> target TAP by holding both <strong>the</strong>hardware nSRST system reset signal and <strong>the</strong> nTRST TAPreset signal LOW.FakeResets <strong>the</strong> system by entering supervisor mode, and setting<strong>the</strong> program counter to <strong>the</strong> address of <strong>the</strong> reset vector(known as a soft reset).Ctrl_Reg The Control register. This reset, in instances whereprocessors have a reset register, enables you to reset <strong>the</strong>processor without using <strong>the</strong> external reset lines. If you set<strong>the</strong> reset type to Ctrl_Reg, <strong>the</strong>n this control register is used.SWO Mode Set to Manchester or UART, depending on <strong>the</strong> target mode.If <strong>the</strong> SWO Mode is set to UART, <strong>the</strong> debug hardware unit is able to detect <strong>the</strong>SWO UART Baud rate.This setting has no effect in Manchester mode.SWO UART Baud rateFor <strong>the</strong> frequency of <strong>the</strong> incoming data. If you set this to 0, <strong>the</strong> system attemptsto autodetect <strong>the</strong> baud rate.NoteUART mode in <strong>the</strong> SWO context also means Non Return to Zero (NRZ) mode.TAP Reset via State TransitionsIf you want <strong>the</strong> JTAG logic in <strong>the</strong> target hardware to be reset by forcing transitionswithin its state machine. This is done in addition to holding <strong>the</strong> nTRST TAP resetsignal LOW. Select this option if nTRST is not connected, or if <strong>the</strong> targethardware requires that you force a reset of <strong>the</strong> JTAG logic whenever resetting.Target nSRST + nTRST linkedIf <strong>the</strong> target hardware has its nSRST and nTRST JTAG signals linked.Use SWJ SwitchingIf this is set, it causes <strong>the</strong> SWJ switching sequence to be sent before connectingto <strong>the</strong> target device. On devices that support SWJ switching, this causes <strong>the</strong> DAPto switch its interface to <strong>the</strong> selected protocol.NoteIf a target supports both JTAG and SWD, you must enable this setting before youautoconfigure that target.<strong>ARM</strong> DUI 0498F Copyright © 2010-2012 <strong>ARM</strong>. All rights reserved. 5-34ID021112Non-Confidential

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