ARM DS-5 Using the Debug Hardware Configuration Utilities

Creating debug hardware target configurations5.18 Debug hardware Advanced configuration settingsDepending on your development platform configuration, a selection of the following controls isavailable in the Advanced settings:Allow ICE to perform TAP resetSet this item to True to allow your debug hardware unit to hold the nSRST lineactive long enough to perform any post-reset setup that might be required after atarget-initiated reset. This can extend the time that the target is held in reset. If thisitem is set to False, your debug hardware unit does not assert the reset line, butpost-reset setup might not be complete before the target starts to run.Allow ICE to latch System ResetSet this item to True to allow your debug hardware unit to perform nTRST resetwhile holding nSRST. This ensures that the Test Access Port (TAP) state machineand associated debug logic is properly reset.LVDS Debug Interface modeThis can be set either to JTAG or SWD. If set to SWD, this causes RVI to connectto the target using the SWD protocol instead of JTAG.nSRST High modeSelects the drive strength used when the reset signal is in the high, or inactive,state. Output can be driven as a strong or weak high, or not driven (tri-state).nTRST High modeSelects the drive strength used when the reset signal is in the high, or inactive,state. Output can be driven as a strong or weak high, or not driven (tri-state).nSRST Low modeSelects the drive strength used when the reset signal is in the low, or active, state.Output can be driven as a strong or weak low, or not driven (tri-state).nTRST Low modeSelects the drive strength used when the reset signal is in the low, or active, state.Output can be driven as a strong or weak low, or not driven (tri-state).nSRST Hold Time (ms)Specifies how long the debug hardware unit holds the hardware nSRST systemreset signal LOW.nTRST Hold Time (ms)Specifies how long the debug hardware unit holds the nTRST TAP reset signalLOW.nSRST Post Reset Delay (ms)Specifies how long after the hardware nSRST system reset before the debughardware unit enters the Post Reset State.nTRST Post Reset Delay (ms)Specifies how long after the nTRST TAP reset before the debug hardware unitenters the Post Reset State.Perform TAP reset on first connectResets the target hardware whenever you connect.ARM DUI 0498F Copyright © 2010-2012 ARM. All rights reserved. 5-33ID021112Non-Confidential